A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Theory and experiment of two-photon 'direct' interference for type-II spontaneous parametric down-conversion with an ultrafast pulse laser pump

Fourth-order spatial interference of entangled photon pairs generated in the process of spontaneous parametric down-conversion pumped by a femtosecond pulse laser has been performed for the first time. In theory, it takes into account the transverse correlation between the two photons and is used to calculate the dependence of the visibility of the interference pattern obtained in Young's double-slit experiment. In this experiment, a short focal length tens and two narrow band interference filters were adopted to eliminate the effects of the broadband pump laser and improve the visibility of the interference pattern under the condition of nearly collinear light and degenerate phase matching.

Capacitance-voltage characteristic as a trace of the exciton evolvement from spatially direct to indirect in quantum wells

We have investigated the photo-excited capacitance-voltage (C-V) characteristics as well as the photoluminescence spectra under different biases of a wide quantum well (QW) embedded in an n(+)-i-n(+) double-barrier structure. The pronounced peak feature at zero bias in the C-V spectrum observed upon illumination is regarded as a kind of quantum capacitance related to the quantum confined Stark effect, originating from the spatial separation of the photo-generated electron and hole gas in the QW. This fact is further demonstrated through the comparison between the C-V curve with the PL intensity versus applied voltage relationship under the same excitation. The results may provide us with a more direct and sensitive means in the detection of the separation and accumulation of both types of free carriers-electrons and holes-in low-dimensional semiconductor structures, especially in a new type of optical memory cell.

Semi-insulating GaAs grown in outer space

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

Outer space grown semi-insulating GaAs and its applications

GaAs single crystal has been grown in recoverable satellite. Hall measurements indicate that the GaAs shows semi-insulating behavior. The structural properties of the crystal have been improved obviously, and their uniformity has been improved as well. The stoichiometry and its distribution in space-grown GaAs are improved greatly compared with the GaAs single crystal grown terrestrially. The properties of integrated circuits made by direct ion-implantation on space-grown GaAs are better than those made on ground-grown materials. These results show that the stoichiometry in semi-insulating GaAs seriously affects the properties of related devices.

A direct-conversion mixer with a DC-offset cancellation for WLAN

This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.

A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

Direct Wafer Bonding Technology employing vacuum-cavity pre-bonding

A novel low temperature direct wafer bonding technology employing vacuum-cavity pre-bonding is proposed and applied in bonding of InGaAs/Si couple wafers under 300 degrees C and InP/GaAs couple wafers under 350 degrees C. Aligning accuracy of 0.5 mu m is achieved. During wafer bonding process the pressure on the couple wafers is 10MPa. The interface energy is sufficiently high to allow thinning of the wafers down from 350um to about 100um. And the tensile strength test indicates the bonding energy of bonded samples is about equal to the bonded samples at 550 degrees C.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

The wideband high-linearity mixers for cable television tuner application

The wideband high-linearity mixers for a double conversion cable TV tuner is presented. The up-conversion mixer converts the input signal from 100MHz to 1000 MHz to the intermediate frequency (IF) of I GHz above. And the down-conversion mixer converts the frequency back. The degeneration resistors are used to Improve the linearity. The tuner is implemented in a 0.35 mu m SiGe technology. Input power at 1dB compression point can reach +14.23dBm. The lowest noise figure is 17.5dB. The two mixers consume 103mW under a supply voltage of 5 V.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.