994 resultados para Amsterdam Architecture Centre


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Background: Effective bed use is crucial to an efficient NHS. Current targets suggest a decrease in mean occupancy as the most appropriate method of improving overall efficiency. The elderly and those suffering from complex medical problems are thought to account for a high proportion of overall bed occupancy.

Aim: To assess the effect of prolonged hospital stay (>100 days) on overall bed occupancy in a modern teaching hospital.

Design: Retrospective analysis.

Methods: Analysis of all admission episodes (n = 117 178) over a five-year period in a large teaching hospital in a single UK region, serving a population of approximately 200 000. A logistic regression multi-factorial model was used to assess the effect of demographic and diagnostic variables on duration of stay.

Results: A prolonged stay (>100 days) was seen in 648 admission episodes (0.6%). These accounted for 11% of the overall bed occupancy over the 5-year period. Excluding all prolonged admission episodes from our analysis made no difference to the overall median length of stay.

Discussion: Prolonged hospitalizations have a significant impact on bed occupancy. Targeting these very long (>100 days) hospital stays may better improve overall efficiency, compared to targeting mean or median length of stay.

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An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

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A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

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A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.