Capability Curve Based Enhanced Reactive Power Control Strategy for Stability Enhancement and Network Voltage Management

Reactive power has become a vital resource in modern electricity networks due to increased penetration of distributed generation. This paper examines the extended reactive power capability of DFIGs to improve network stability and capability to manage network voltage profile during transient faults and dynamic operating conditions. A coordinated reactive power controller is designed by considering the reactive power capabilities of the rotor-side converter (RSC) and the grid-side converter (GSC) of the DFIG in order to maximise the reactive power support from DFIGs. The study has illustrated that, a significant reactive power contribution can be obtained from partially loaded DFIG wind farms for stability enhancement by using the proposed capability curve based reactive power controller; hence DFIG wind farms can function as vital dynamic reactive power resources for power utilities without commissioning additional dynamic reactive power devices. Several network adaptive droop control schemes are also proposed for network voltage management and their performance has been investigated during variable wind conditions. Furthermore, the influence of reactive power capability on network adaptive droop control strategies has been investigated and it has also been shown that enhanced reactive power capability of DFIGs can substantially improve the voltage control performance.

Voltage and power quality improvement strategy for a DFIG wind turbine during variable wind conditions

This paper presents a voltage and power quality enhancement scheme for a doubly-fed induction generator (DFIG) wind farm during variable wind conditions. The wind profiles were derived considering the measured data at a DFIG wind farm located in Northern Ireland (NI). The aggregated DFIG wind farm model was validated using measured data at a wind farm during variable generation. The voltage control strategy was developed considering the X/R ratio of the wind farm feeder which connects the wind farm and the grid. The performance of the proposed strategy was evaluated for different X/R ratios, and wind profiles with different characteristics. The impact of flicker propagation along the wind farm feeder and effectiveness of the proposed strategy is also evaluated with consumer loads connected to the wind farm feeder. It is shown that voltage variability and short-term flicker severity is significantly reduced following implementation of the novel strategy described.

Voltage Dip Benchmarking in Power Quality and Disturbance Monitoring

This paper examines power quality benchmarks in the electricity supply industry (ESI) and impact of standards for the reduction of voltage dip incidents. The paper considers adherence to particular standards and is supported by several case studies from incidents where voltage dips have been detected and assessed by the power systems division of Scottish Power and where improvements have been implemented to help militate against subsequent incidents.

Accurate and Efficient Modelling to Calculate the Voltage Dependence of Liquid Crystal Based Reflectarray Cells

Two models that can predict the voltage-dependent scattering from liquid crystal (LC)-based reflectarray cells are presented. The validity of both numerical techniques is demonstrated using measured results in the frequency range 94-110 GHz. The most rigorous approach models, for each voltage, the inhomogeneous and anisotropic permittivity of the LC as a stratified media in the direction of the biasing field. This accounts for the different tilt angles of the LC molecules inside the cell calculated from the solution of the elastic problem. The other model is based on an effective homogeneous permittivity tensor that corresponds to the average tilt angle along the longitudinal direction for each biasing voltage. In this model, convergence problems associated with the longitudinal inhomogeneity are avoided, and the computation efficiency is improved. Both models provide a correspondence between the reflection coefficient (losses and phase-shift) of the LC-based reflectarray cell and the value of biasing voltage, which can be used to design beam scanning reflectarrays. The accuracy and the efficiency of both models are also analyzed and discussed.

Voltage Controlled Intertwined Spiral Arrays for Reconfigurable Metasurfaces

Reconfigurable bistate metasurfaces composed of interwoven spiral arrays with embedded pin diodes are proposed for single and dual polarisation operation. The switching capability is enabled by pin diodes that change the array response between transmission and reflection modes at the specified frequencies. The spiral conductors forming the metasurface also supply the dc bias for controlling pin diodes, thus avoiding the need of additional bias circuitry that can cause parasitic interference and affect the metasurface response. The simulation results show that proposed active metasurfaces exhibit good isolation between transmission and reflection states, while retaining excellent angular and polarisation stability with the large fractional bandwidth (FBW) inherent to the original passive arrays. © 2014 A. Vallecchi et al.

Mechanisms and sources of passive intermodulation in printed circuits

Modern wireless systems are expected to operate in multiple frequency bands and support diverse communications standards to provide the high volume and speed of data transmission. Today's major limitations of their performance are imposed by interference, spurious emission and noise generated by high-power carriers in antennas and passive components of the RF front-end. Passive Intermodulation (PIM), which causes the combinatorial frequency generation in the operational bands, presents a primary challenge to signal integrity, system efficacy and data throughput. © 2013 IEEE.

Holistic design of 8-way combining transformers in SiGe technology for use in millimetre-wave power amplifiers

This paper presents the design of a novel 8-way power-combining transformer for use in mm-wave power amplifier (PA). The combiner exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. A complete circuit comprised of a power splitter, two-stage cascode PA array, a power combiner and input/output matching elements was designed and realized in SiGe technology. Measured gain of at least 16.8 dB was obtained from 76.4 GHz to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm OP and 14 dBm saturated output power when operated from a 3.2 V DC supply voltage at 78 GHz. © 2013 IEEE.

Distribution Network Voltage Support Using Sensitivity-based Dispatch of Distributed Generation

This paper is concerned with the voltage and reactive power issues surrounding the connection of Distributed Generation (DG) on the low-voltage (LV) distribution network. The presented system-wide voltage control algorithm consists of three stages. Firstly available reactive power reserves are utilized. Then, if required, DG active power output is curtailed. Finally, curtailment of non-critical site demand is considered. The control methodology is tested on a variant of the 13-bus IEEE Node Radial Distribution Test Feeder. The presented control algorithm demonstrated that the distribution system operator (DSO) can maintain voltage levels within a desired statutory range by dispatching reactive power from DG or network devices. The practical application of the control strategy is discussed.

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration system level interactions and ensuring that under any change of operating conditions only the "lesscrucial" computations, that contribute less to block/system output quality, are affected. The design methodology applied to a DCT/IDCT system shows large power benefits (up to 69%) at reasonable image quality while tolerating errors induced by varying operating conditions (VOS, process variations, channel noise). Interestingly, the proposed IDCT scheme conceals channel noise at scaled voltages. ©2009 IEEE.

Voltage over-scaling:A cross-layer design perspective for energy efficient systems

Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.