Sensing of delaminations in composite laminates using embedded magnetostrictive particle layers

This is an exploratory study to illustrate the feasibility of detecting delamination type of damage in polymeric laminates with one layer of magnetostrictive particles. One such beam encircled with excitation and sensing coils is used for this study. The change in stress gradient of the magnetostrictive layer in the vicinity of delamination shows up as a change in induced voltage in the sensing coil, and therefore provides a means to sense the presence of delamination. Recognizing the constitutive behavior of the Terfenol-D material is highly nonlinear, analytical expressions for the constitutive relations are developed by using curve fitting techniques to the experimental data. Analytical expressions that relate the applied excitation field with the stress and magnetic flux densities induced in the magnetostrictive layer are developed. Numerical methods are used to find the relative change in the induced voltage in the sensing coil due to the presence of delamination. A typical example of unidirectional laminate, with embedded delaminations, is used for the simulation purposes. This exploratory study illustrates that the open-circuit voltage induced in the sensing coil changes significantly (as large of 68 millivolts) with the occurrence of delamination. This feature can be exploited for device off-line inspection techniques and/or linking monitoring procedures for practical applications.

Capacitive-Resistive Transients in terms of field quantities

Capacitive-resistive transients in extended media are discussed in tenns of electric field quantities. Obviously, in rhese problems, the contribution of the magnetlc field to the electric field is deemed negligible. For a simple lllusfratlve example, the field solution is compared with the circuit-theoretical resuit for the voltage and current. An algorithm for solving such transients in space and time doman with the help of a Laplace solver is presented. Any other Laplace solver can also be used far this purpose. Its applicability is demonstrated with three examples, one of which is chosen to have a circuit-theoretical solution.

Dodecagonal space vector diagram using cascaded H-Bridge inverters

This paper proposes the development of dodecagonal (12-sided) space vector diagrams from cascaded H-Bridge inverters. As already reported in literatures, dodecagonal space vector diagrams have many advantages over conventional hexagonal ones. Some of them include the absence of 6n±1, (n=odd) harmonics from the phase voltage, and the extension of the linear modulation range. In this paper, a new power circuit is proposed for generating multiple dodecagons in the space vector plane. It consists of two cascaded H-Bridge cells fed from asymmetric dc voltage sources. It is shown that, with proper PWM timing calculation and placement of active and zero vectors, a very high quality of sine-wave can be produced. At the same time, the switching frequency of individual cells can be reduced substantially. Detailed PWM analysis, one design example and an elaborate simulation study is presented to support the proposed idea.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Electrical characterization of Ba(Zr0.1Ti0.9)O-3 thin films grown by pulsed laser ablation technique

In situ annealed thin films of ferroelectric Ba(Zr0.1Ti0.9)O-3 were deposited on platinum substrates by pulsed laser ablation technique. The as grown films were polycrystalline in nature without the evidence of any secondary phases. The polarization hysteresis loop confirmed the ferroelectricity, which was also cross-checked with the capacitance-voltage characteristics. The remnant polarization was about 5.9 muC cm(-2) at room temperature and the coercive field was 45 kV. There was a slight asymmetry in the hysteresis for different polarities, which was thought to be due to the work function differences of different electrodes. The dielectric constant was about 452 and was found to exhibit low frequency dispersion that increased with frequency, This was related to the space-charge polarization. The complex impedance was plotted and this exhibited a semicircular trace, and indicated an equivalent parallel R - C circuit within the sample. This was attributed to the grain response. The DC leakage current-voltage plot was consistent with the space-charge limited conduction theory, but showed some deviation, which was explained by assuming a Poole-Frenkel type conduction to be superimposed on to the usual space-charge controlled current. (C) 2002 Elsevier Science B.V. All rights reserved.

Starting scheme for load commutated inverter-fed wound field synchronous machine using an auxiliary low-power voltage source inverter

Conventional thyristor-based load commutated inverter (LCI)-fed wound field synchronous machine operates only above a minimum speed that is necessary to develop enough back emf to ensure commutation. The drive is started and brought up to a speed of around 10-15% by a complex `dc link current pulsing' technique. During this process, the drive have problems such as pulsating torque, insufficient average starting torque, longer starting time, etc. In this regard a simple starting and low-speed operation scheme, by employing an auxiliary low-power voltage source inverter (VSI) between the LCI and the machine terminals, is presented in this study. The drive is started and brought up to a low speed of around 15% using the VSI alone with field oriented control. The complete control is then smoothly and dynamically transferred to the conventional LCI control. After the control transfer, the VSI is turned off and physically disconnected from the main circuit. The advantages of this scheme are smooth starting, complete control of torque and flux at starting and low speeds, less starting time, stable operation, etc. The voltage rating of the required VSI is very low of the order of 10-15%, whereas the current rating is dependent on the starting torque requirement of the load. The experimental results from a 15.8 hp LCI-fed wound field synchronous machine are given to demonstrate the scheme.

Circuits on cylinders

We consider the computational power of constant width polynomial size cylindrical circuits and non deterministic branching programs. We show that every function computed by a Pi(2) o MOD o AC(0) circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching program (or cylindrical circuit) and that every function computed by a constant width polynomial size cylindrical circuit belongs to ACC(0).

An asymmetric cascaded H-Bridge inverters for generating 12-sided polygonal space vector diagrams for Motor drives

A new topology of asymmetric cascaded H-Bridge inverter is presented in this paper It consists of two cascaded H-bridge cells per phase. They are fed from isolated dc sources having a dc bus ratio of 1:0.366. Out of many space vectors possible from this circuit, only those are chosen that lie on 12-sided polygons. Thus, the overall space vector diagram produced by this circuit consists of multiple numbers of 12-sided polygons. With a proper PWM timing calculations based on these selected space vectors, it is possible to eliminate all the 6n +/- 1, (n = odd) harmonics from the phase voltage under all operating conditions. The switching frequency of individual H-Bridge cells is also substantially low. Extensive experimental results have been presented in this paper to validate the proposed concept.

The Effect of Evacuated Backside Cavity on the Dynamic Characteristics of a Capacitive Micromachined Ultrasonic Transducer

In this paper, we investigate the effect of vacuum sealing the backside cavity of a Capacitive Micromachined Ultrasonic Transducer (CMUT). The presence or absence of air inside the cavity has a marked effect upon the system parameters, such as the natural frequency, damping, and the pull-in voltage. The presence of vacuum inside the cavity of the device causes a reduction in the effective gap height which leads to a reduction in the pull-in voltage. We carry out ANSYS simulations to quantify this reduction. The presence of vacuum inside the cavity of the device causes stress stiffening of the membrane, which changes the natural frequency of the device. A prestressed modal analysis is carried out to determine the change in natural frequency due to stress stiffening. The equivalent circuit method is used to evaluate the performance of the device in the receiver mode. The lumped parameters of the device are obtained and an equivalent circuit model of the device is constructed to determine the open circuit receiving sensitivity of the device. The effect of air in the cavity is included by incorporating an equivalent compliance and an equivalent resistance in the equivalent circuit.

On synthesis of easily testable (k, K) circuits

A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.

Acquisition time improvement of PLLs using some aiding functions

Analytical studies are carried out to minimize acquisition time in phase-lock loop (PLL) applications using aiding functions. A second order aided PLL is realized with the help of the quasi-stationary approach to verify the acquisition behavior in the absence of noise. Time acquisition is measured both from the study of the LPF output transient and by employing a lock detecting and indicating circuit to crosscheck experimental and analytical results. A closed form solution is obtained for the evaluation of the time acquisition using different aiding functions. The aiding signal is simple and economical and can be used with state of the art hardware.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation

Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.