Simulated superior performance of superjuction bipolar transistors

This paper presents for the first time an investigation and comparison of the superjunction IGBT (SJBT) as proposed in [1,2] and the current state of art Field Stop IGBT [3,4]. Simulation results indicate the superior performance of the superjunction IGBT under switching conditions. For the same conditions, at a collector current density of 100A/cm2 and on-state voltage 1.6 V the switching off losses for a SJBT and Field-Stop IGBT are 1 and 4.5 mJ/cm 2 respectively. © 2006 IEEE.

Investigation into IGBT dV/dt during turn-off and its temperature dependence

In many power converter applications, particularly those with high variable loads, such as traction and wind power, condition monitoring of the power semiconductor devices in the converter is considered desirable. Monitoring the device junction temperature in such converters is an essential part of this process. In this paper, a method for measuring the insulated gate bipolar transistor (IGBT) junction temperature using the collector voltage dV/dt at turn-OFF is outlined. A theoretical closed-form expression for the dV/dt at turn-OFF is derived, closely agreeing with experimental measurements. The role of dV/dt in dynamic avalanche in high-voltage IGBTs is also discussed. Finally, the implications of the temperature dependence of the dV/dt are discussed, including implementation of such a temperature measurement technique. © 2006 IEEE.

Effect of bandgap narrowing on performance of modern power devices

The effect of the bandgap narrowing (BGN) on performance of power devices is investigated in detail in this paper. The analysis reveals that the change in the energy band structure caused by BGN can strongly affect the conductivity modulation of the bipolar devices resulting in a completely different performance. This is due to the modified injection efficiency under high-level injection conditions. Using a comprehensive analysis of the injection efficiency in a p-n junction, an analytical model for this phenomenon is developed. BGN model tuning has been proved to be essential in accurately predicting the performance of a lateral insulated-gate bipolar transistor (IGBT). Other devices such as p-i-n diodes or punch-through IGBTs are significantly affected by the BGN, while others, such as field-stop IGBTs or power MOSFETs, are only marginally affected. © 2013 IEEE.

Zn-doped InGaAs Base Heterojunction Bipolar Transistors Grown by Low Pressure Metal Organic Chemical Vapor Deposition

High performance InP/InGaAs heterojunction bipolar transistors(HBTs) have been widely used in high-speed electronic devices and optoelectronic integrated circuits. InP-based HBTs were fabricated by low pressure metal organic chemical vapor deposition(MOCVD) and wet chemical etching. The sub-collector and collector were grown at 655 ℃ and other layers at 550 ℃. To suppress the Zn out-diffusion in HBT, base layer was grown with a 16-minute growth interruption. Fabricated HBTs with emitter size of 2.5×20 μm~2 showed current gain of 70~90, breakdown voltage(BV_(CE0))>2 V, cut-off frequency(f_T) of 60 GHz and the maximum relaxation frequency(f_(MAX)) of 70 GHz.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Design, Manufacture and Performance of Germanium Bipolar Transistors

Germanium NPN bipolar transistors have been manufactured using phosphorus and boron ion implantation processes. Implantation and subsequent activation processes have been investigated for both dopants. Full activation of phosphorus implants has been achieved with RTA schedules at 535?C without significant junction diffusion. However, boron implant activation was limited and diffusion from a polysilicon source was not practical for base contact formation. Transistors with good output characteristics were achieved with an Early voltage of 55V and common emitter current gain of 30. Both Silvaco process and device simulation tools have been successfully adapted to model the Ge BJT(bipolar junction transistor) performance.

Multiobjective design optimization of IGBT power modules considering power cycling and thermal cycling

Insulated-gate bipolar transistor (IGBT) power modules find widespread use in numerous power conversion applications where their reliability is of significant concern. Standard IGBT modules are fabricated for general-purpose applications while little has been designed for bespoke applications. However, conventional design of IGBTs can be improved by the multiobjective optimization technique. This paper proposes a novel design method to consider die-attachment solder failures induced by short power cycling and baseplate solder fatigue induced by the thermal cycling which are among major failure mechanisms of IGBTs. Thermal resistance is calculated analytically and the plastic work design is obtained with a high-fidelity finite-element model, which has been validated experimentally. The objective of minimizing the plastic work and constrain functions is formulated by the surrogate model. The nondominated sorting genetic algorithm-II is used to search for the Pareto-optimal solutions and the best design. The result of this combination generates an effective approach to optimize the physical structure of power electronic modules, taking account of historical environmental and operational conditions in the field.

In situ diagnostics and prognostics of wire bonding faults in IGBT modules for electric vehicle drives

This paper presents a diagnostic and prognostic condition monitoring method for insulated-gate bipolar transistor (IGBT) power modules for use primarily in electric vehicle applications. The wire-bond-related failure, one of the most commonly observed packaging failures, is investigated by analytical and experimental methods using the on-state voltage drop as a failure indicator. A sophisticated test bench is developed to generate and apply the required current/power pulses to the device under test. The proposed method is capable of detecting small changes in the failure indicators of the IGBTs and freewheeling diodes and its effectiveness is validated experimentally. The novelty of the work lies in the accurate online testing capacity for diagnostics and prognostics of the power module with a focus on the wire bonding faults, by injecting external currents into the power unit during the idle time. Test results show that the IGBT may sustain a loss of half the bond wires before the impending fault becomes catastrophic. The measurement circuitry can be embedded in the IGBT drive circuits and the measurements can be performed in situ when the electric vehicle stops in stop-and-go, red light traffic conditions, or during routine servicing.

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

A Novel VSI- and CSI-Fed Dual Stator Induction Motor Drive Topology for Medium-Voltage Drive Applications

A new configuration is proposed for high-power induction motor drives. The induction machine is provided with two three-phase stator windings with their axes in line. One winding is designed for higher voltage and is meant to handle the main (active) power. The second winding is designed for lower voltage and is meant to carry the excitation (reactive) power. The excitation winding is powered by an insulated-gate-bipolar-transistor-based voltage source inverter with an output filter. The power winding is fed by a load-commutated current source inverter. The commutation of thyristors in the load-commutated inverter (LCI) is achieved by injecting the required leading reactive power from the excitation inverter. The MMF harmonics due to the LCI current are also cancelled out by injecting a suitable compensating component from the excitation inverter, so that the electromagnetic torque of the machine is smooth. Results from a prototype drive are presented to demonstrate the concept.