Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform

Numerical Linear Algebra (NLA) kernels are at the heart of all computational problems. These kernels require hardware acceleration for increased throughput. NLA Solvers for dense and sparse matrices differ in the way the matrices are stored and operated upon although they exhibit similar computational properties. While ASIC solutions for NLA Solvers can deliver high performance, they are not scalable, and hence are not commercially viable. In this paper, we show how NLA kernels can be accelerated on REDEFINE, a scalable runtime reconfigurable hardware platform. Compared to a software implementation, Direct Solver (Modified Faddeev's algorithm) on REDEFINE shows a 29X improvement on an average and Iterative Solver (Conjugate Gradient algorithm) shows a 15-20% improvement. We further show that solution on REDEFINE is scalable over larger problem sizes without any notable degradation in performance.

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n × n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array.

Multi-Port Network Approach for the Analysis of Dual Band Fractal Microstrip Antennas

The multiport network approach is extended to analyze the behavior of microstrip fractal antennas. The capacitively fedmicrostrip square ring antenna has the side opposite to the feed arm replaced with a fractal Minkowski geometry. Dual frequency operation is achieved by suitably choosing the indentation of this fractal geometry. The width of the two sides adjacent to this is increased to further control the resonant characteristics and the ratio of the two resonance frequencies of this antenna. The impedance matrix for the multiport network model of this antenna is simplified exploiting self-similarity of the geometry with greater accuracy and reduced analysis time. Experimentally validated results confirm utility of the approach in analyzing the input characteristics of similar multi-frequency fractal microstrip antennas with other fractal geometries.

Studies on Ultra Wideband Triangular Patch Antennas for Imaging Applications

This paper presents simulation and experimental studies on the characterization of ultra wideband antennas for imaging applications. Various configurations of antennas were simulated for their time and frequency domain characteristics with special emphasis on flat responses for group delay and gain versus frequency. Parametric studies reported here showed that locating the capacitive feed strip near the vertex of the triangle gave better response in these respects. An antenna with operating frequency from 2.9GHz to 4.1GHz was fabricated and measured.

Multifunctional microstrip antennas for wireless applications

Some possibilities of Antenna designs for multifunctional wireless terminals are presented here. A ring antenna with an electromagnetically coupled feed has been extended to systematically design a multi-frequency antenna using multiple rings. A variant of this approach uses one single ring with fractal and widened segments to design dual frequency antenna with choice of resonant frequencies. A different approach based on U-shaped slots is used for designing an antenna for onboard wireless applications, making use of materials presently used in a typical airplane. Several discrete bands up to 6 GHz, widely used for various standards are covered in this single-feed antenna.

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. (C) 2014 Elsevier B.V. All rights reserved.

Interference Alignment With Diversity for the 2 x 2 X-Network With Four Antennas

A transmission scheme based on the Alamouti code, which we call the Li-Jafarkhani-Jafar (LJJ) scheme, was recently proposed for the 2 x 2 X-network i.e., two-transmitter (Tx) two-receiver X-network] with two antennas at each node. This scheme was claimed to achieve a sum degrees of freedom (DoF) of 8/3 and also a diversity gain of two when fixed finite constellations are employed at each Tx. Furthermore, each Tx required the knowledge of only its own channel unlike the Jafar-Shamai scheme which required global CSIT to achieve the maximum possible sum DoF of 8/3. In this paper, we extend the LJJ scheme to the 2 x 2 X-network with four antennas at each node. The proposed scheme also assumes only local channel knowledge at each Tx. We prove that the proposed scheme achieves the maximum possible sum DoF of 16/3. In addition, we also prove that, using any fixed finite constellation with appropriate rotation at each Tx, the proposed scheme achieves a diversity gain of at least four.

Differential Multi-phase DLL for Reconfigurable Radio Frequency Synthesizer

A multi phase, delay-locked loop (DLL) based frequency synthesizer is designed for harmonic rejection mixing in reconfigurable radios. This frequency synthesizer uses a 1 GHz input reference frequency, and achieves <= 20ns settling time by utilizing a wide loop bandwidth. The circuit has been designed in 0.13-mu m CMOS technology. It is designed for a frequency range of 500 MHz to 3 GHz with stuck/harmonic lock removal assist. Index Terms-stuck lock, harmonic lock, delay-locked loops, multi phase, phase detector, frequency synthesis

Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath

In this paper we present HyperCell as a reconfigurable datapath for Instruction Extensions (IEs). HyperCell comprises an array of compute units laid over a switch network. We present an IE synthesis methodology that enables post-silicon realization of IE datapaths on HyperCell. The synthesis methodology optimally exploits hardware resources in HyperCell to enable software pipelined execution of IEs. Exploitation of temporal reuse of data in HyperCell results in significant reduction of input/output bandwidth requirements of HyperCell.

Identification of type and degree of railway ballast fouling using ground coupled GPR antennas

GPR is widely used for ballast fouling identification, however, there are no robust guidelines to find the degree and type of fouling quantitatively. In this study, GPR studies were carried out on model and actual railway tracks using three ground coupled antennas and considering three fouling materials. Three ground coupled antennas viz., 100 MHz, 500 MHz and 800 MHz antennas were used for the initial survey and it was found that the 800 MHz ground coupled antenna is an optimum one to get quality results. Three major fouling materials viz., screened/broken ballast, coal and iron ore were used to construct prototype model sections, which were 1/2 of the actual Indian broad-gauge railway track. A separate model section has been created for each degree and type of fouling and GPR surveys were carried out. GPR study shows that increasing the fouling content results in a decrease in the Electromagnetic Wave (EMW) velocity and an increase in the dielectric constant. EMW velocity of ballast fouled with screened ballast was found to be more than coal fouled ballast and iron ore fouled ballast at any degree of fouling and EMW velocity of iron ore fouled ballast was found to be less than coal and screen ballast fouled ballast. Dielectric constant of iron ore fouled ballast was found to be higher than coal and screen ballast fouled ballast for all degrees of fouling. Average slope of the trend line of screen ballast fouled section is low (25.6 degrees), coal fouled ballast is medium (27.8 degrees) and iron ore fouled ballast is high (47.6 degrees). (C) 2016 Elsevier B.V. All rights reserved.