DEVELOPMENT OF THE WAVE CONTOURING RAFT.

The wave contouring raft system is the outcome of ideas initiated and developed by Sir Christopher Cockerell from 1972 onwards. His objective was to develop a wave energy device which is within the bounds of current technology. It should consist of simple, relatively small units, amenable to quantity production, which would enable a power generating system to be built up and commissioned in stages according to needs and production capability. This thinking led to the investigation of chains of pontoons, hinged together so that the passage of a wave down the chain causes the pontoons to oscillate relative to one another. Energy is extracted from the sea by applying a torque about the hinges to damp the motion. The work has involved extensive model testing in wave tanks and the building and testing of a 3-unit 1/10 scale power generating installation in the Solent, as well as design studies for a full size installation for Atlantic conditions.

Vibration and stress analysis in the presence of structural uncertainty

At medium to high frequencies the dynamic response of a built-up engineering system, such as an automobile, can be sensitive to small random manufacturing imperfections. Ideally the statistics of the system response in the presence of these uncertainties should be computed at the design stage, but in practice this is an extremely difficult task. In this paper a brief review of the methods available for the analysis of systems with uncertainty is presented, and attention is then focused on two particular "non- parametric" methods: statistical energy analysis (SEA), and the hybrid method. The main governing equations are presented, and a number of example applications are considered, ranging from academic benchmark studies to industrial design studies. © 2009 IOP Publishing Ltd.

Function propagation through nested systems

Concepts of function are central to design but statements about a device's functions can be interpreted in different ways. This raises problems for researchers trying to clarify the foundations of design theory and for those developing design support-tools that can represent and reason about function. By showing how functions relate systems to their sub-systems and super-systems, this article illustrates some limitations of existing function terminology and some problems with existing function statements. To address these issues, a system-relative function terminology is introduced. This is used to demonstrate that systems function not only with respect to their most local super-system, but also with respect to their more global super-systems. © 2012 Elsevier Ltd. All rights reserved.

SFC新中心区及10MeV质子回旋加速器的设计

本文比较系统地介绍了扇聚焦等时性回旋加速器内部的束流动力学理论，并刘其中心区设计的方法加以阐明。给出了作者所做的两个具体的设计。第一章系统地介绍了扇聚焦等时性回旋加速器的基本理论，包括等时性加速原理，轴向聚焦的获得，静态平衡轨道和等时性磁场的求解，共振理论，并简单介绍了加速轨道的一些性质。第二章介绍了扇聚焦等时性回旋加速器的一些注入方法及中心区设计的思路。重点放在内离子源束流注入及中心区的设计和外离子源来的束流的轴向注入及中心区的设计上。列出了轴向注入时常用的静电偏转镜的类型并对其加以简介。第三章介绍了SFC新中心区的设计。新中心区是为SFC加速荷质比小的重离子而设计的，在SFC采用三次谐波模式加速时，将注入半径由3．ocm提高到3．6cm。它包括中心区电极形状的设计，中心区加速轨道的计算及中心区相空间接受度的获得。第四章介绍了10MeV质子等时性回旋加速器的设计。给出了等时性磁场的垫补方法，内离子源注入的中心区设计，并计算了质子从离子源引出后加速到10MeV能量的加速轨道，得到其束流性质。论文的最后部分简单总结了本文的工作，并提出了今后工作的设想。

Subpixel interpolation architecture for multistandard video motion estimation

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.

Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Reconfigurable full-search video motion estimation architecture

In this paper, a new reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation and a standard-cell based chip design study is presented. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.263, H.264, AVS and WMV-9. The architecture exhibits simpler control, high throughput and relative low hardware cost and highly competitive when compared with excising designs for specific video standards. It can also, through the use of control signals, be dynamically reconfigured at run-time to accommodate different system constraint such as the trade-off in power dissipation and video-quality. The computational rates achieved make the circuit suitable for high end video processing applications. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.

Multi-standard sub-pixel interpolation architecture for video motion estimation

A new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video Motion Estimation (ME) is presented. The mixed use of parallel and serial-input FIR filters achieves high throughput rate and efficient silicon utilisation. Flexibility has been achieved by using a multiplexed reconfigurable data-path controlled by a selection signal. Silicon design studies show that this can be implemented using 34.8K gates with area and performance that compares very favourably with existing fixed solutions based solely on the H.264 standard. ©2008 IEEE.

Synthesizable high performance adaptive equaliser and viterbi decoder for the class-IV PRML channel

The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

I Cling to Virtue

Kular’s work centres on design as a means of engaging with social and cultural issues. Commissioned and exhibited by the V&A Museum, this was a mixed-media collection revealing the trajectories of the Lövy-Singh clan, a fictional East London family of mixed descent. It comprised 26 sculptures and two video pieces, developing the previous explorations of the MacGuffin in narrative (Kular REF Output 2). A catalogue with 28 fictional reminiscences, a genealogy and time line positioned the family’s experiences in geographical locations and historical events. Novel use of rapid-prototyping co-opted an industry process to confuse the experience of artefact and artifice. The design explored the historical, literary and cinematic traditions of the family saga and its relationship to memory and artefact. It presented an archive of objects derived from the flawed, biased memory of the (fictional) curator. A coherent story is replaced by one that is multiple and fragmentary. Kular and Toran (RCA) ‘produced’ the family by mixing their own genealogies with those of renowned 20th-century families, both real and fictional, such as the Magnificent Ambersons and the Rothschilds, positioning family members in everyday situations or key historical moments represented by an object and a ‘memory’ triggered by the object. Concept development was undertaken jointly by Kular and Toran. Kular’s archive research emphasised commonwealth immigrant histories and British 20th-century political events. His production contribution was in 3D modelling, rapid prototyping and display, leading production of the two films and development and editing of the narrative texts. The work was accompanied by a catalogue (2011), was reviewed in ICON Magazine (2010), discussed in an article by Hayward, Jones, Toran and Kular in Design and Culture (2013), and featured in The White Review (No. 2). It was re-exhibited in the group show ‘Politique Fiction’ at la Cité du design, Saint-Étienne, France (2013).