CMOS-Compatible and Scalable Deposition of Nanocrystalline Zinc Ferrite Thin Film to Improve Inductance Density of Integrated RF Inductor

Development towards the combination of miniaturization and improved functionality of RFIC has been stalled due to the lack of high-performance integrated inductors. To meet this challenge, integration of magnetic material with high permeability as well as low conductivity is a must. Ferrite films are excellent candidates for RF devices due to their low cost, high resistivity, and low eddy current losses. Unlike its bulk counterpart, nanocrystalline zinc ferrite, because of partial inversion in the spinel structure, exhibits novel magnetic properties suitable for RF applications. However, most scalable ferrite film deposition processes require either high temperature or expensive equipment or both. We report a novel low temperature (< 200 degrees C) solution-based deposition process for obtaining high quality, polycrystalline zinc ferrite thin films (ZFTF) on Si (100) and on CMOS-foundry-fabricated spiral inductor structures, rapidly, using safe solvents and precursors. An enhancement of up to 20% at 5 GHz in the inductance of a fabricated device was achieved due to the deposited ZFTF. Substantial inductance enhancement requires sufficiently thick films and our reported process is capable of depositing smooth, uniform films as thick as similar to 20 mu m just by altering the solution composition. The method is capable of depositing film conformally on a surface with complex geometry. As it requires neither a vacuum system nor any post-deposition processing, the method reported here has a low thermal budget, making it compatible with modern CMOS process flow.

Observation of trap-assisted space charge limited conductivity in short channel MoS2 transistor

We present temperature dependent I-V measurements of short channel MoS2 field effect devices at high source-drain bias. We find that, although the I-V characteristics are ohmic at low bias, the conduction becomes space charge limited at high V-DS, and existence of an exponential distribution of trap states was observed. The temperature independent critical drain-source voltage (V-c) was also determined. The density of trap states was quantitatively calculated from V-c. The possible origin of exponential trap distribution in these devices is also discussed. (C) 2013 AIP Publishing LLC.

A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon metal-oxide-semiconductor field effect transistor

In this work, we present a study on the negative differential resistance (NDR) behavior and the impact of various deformations (like ripple, twist, wrap) and defects like vacancies and edge roughness on the electronic properties of short-channel MoS2 armchair nanoribbon MOSFETs. The effect of deformation (3 degrees-7 degrees twist or wrap and 0.3-0.7 angstrom ripple amplitude) and defects on a 10 nm MoS2 ANR FET is evaluated by the density functional tight binding theory and the non-equilibrium Green's function approach. We study the channel density of states, transmission spectra, and the I-D-V-D characteristics of such devices under the varying conditions, with focus on the NDR behavior. Our results show significant change in the NDR peak to valley ratio and the NDR window with such minor intrinsic deformations, especially with the ripple. (C) 2013 AIP Publishing LLC.

Performance analysis of boron nitride embedded armchair graphene nanoribbon metal-oxide-semiconductor field effect transistor with Stone Wales defects

We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width similar to 5 nm, the simulated ON current is found to be in the range of 265 mu A-280 mu A with an ON/OFF ratio 7.1 x 10(6)-7.4 x 10(6) for a V-DD = 0.68 V corresponding to 10 nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%. (C) 2014 AIP Publishing LLC.

Observation of localized states in atomically thin MoS2 field effect transistor

We present electrical transport arid low frequency (1/f) noise measurements on mechanically exfoliated single, In and triLayer MoS2-based FPI devices on Si/SiO2 substrate. We find that tie electronic states hi MoS2 are localized at low temperatures (T) and conduction happens through variable range hopping (VRH). A steep increase of 1/f noise with decreasing T, typical for localized regime was observed in all of our devices. From gate voltage dependence of noise, we find that the noise power is inversely proportional to square of the number density (proportional to 1/n(2)) for a wide range of T, indicating number density fluctuations to be the dominant source of 1/f noise in these MoS2 FETs.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

Integrating AlGaN/GaN high electron mobility transistor with Si: A comparative study of integration schemes

AlGaN/GaN high electron mobility transistor stacks deposited on a single growth platform are used to compare the most common transition, AlN to GaN, schemes used for integrating GaN with Si. The efficiency of these transitions based on linearly graded, step graded, interlayer, and superlattice schemes on dislocation density reduction, stress management, surface roughness, and eventually mobility of the 2D-gas are evaluated. In a 500 nm GaN probe layer deposited, all of these transitions result in total transmission electron microscopy measured dislocations densities of 1 to 3 x 10(9)/cm(2) and <1 nm surface roughness. The 2-D electron gas channels formed at an AlGaN-1 nm AlN/GaN interface deposited on this GaN probe layer all have mobilities of 1600-1900 cm(2)/V s at a carrier concentration of 0.7-0.9 x 10(13)/cm(2). Compressive stress and changes in composition in GaN rich regions of the AlN-GaN transition are the most effective at reducing dislocation density. Amongst all the transitions studied the step graded transition is the one that helps to implement this feature of GaN integration in the simplest and most consistent manner. (C) 2015 AIP Publishing LLC.

Experimental characterisation and performance evaluation of a coaxial current transformer for measurement of insulated gate bipolar transistor switching current

Measurement of device current during switching characterisation of an insulated gate bipolar transistor (IGBT) requires a current sensor with low insertion impedance and high bandwidth. This study presents an experimental procedure for evaluating the performance of a coaxial current transformer (CCT), designed for the above purpose. A prototype CCT, which can be mounted directly on a power terminal of a 1200 V/50 A half-bridge IGBT module, is characterised experimentally. The measured characteristics include insertion impedance, gain and phase of the CCT at different frequencies. The bounds of linearity within which the CCT can operate without saturation are determined theoretically, and are also verified experimentally. The experimental study on linearity of the CCT requires a high-amplitude current source. A proportional-resonant (PR) controller-based current-controlled half-bridge inverter is developed for this purpose. A systematic procedure for selection of PR controller parameters is also reported in this study. This set-up is helpful to determine the limit of linearity and also to measure the frequency response of the CCT at realistic amplitudes of current in the low-frequency range.

Instability in an amorphous In-Ga-Zn-O field effect transistor upon water exposure

The instability of an amorphous indium-gallium-zinc oxide (IGZO) field effect transistor is investigated upon water treatment. Electrical characteristics are measured before, immediately after and a few days after water treatment in ambient as well as in vacuum conditions. It is observed that after a few days of water exposure an IGZO field effect transistor (FET) shows relatively more stable behaviour as compared to before exposure. Transfer characteristics are found to shift negatively after immediate water exposure and in vacuum. More interestingly, after water exposure the off current is found to decrease by 1-2 orders of magnitude and remains stable even after 15 d of water exposure in ambient as well as in vacuum, whereas the on current more or less remains the same. An x-ray photoelectron spectroscopic study is carried out to investigate the qualitative and quantitative analysis of IGZO upon water exposure. The changes in the FET parameters are evaluated and attributed to the formation of excess oxygen vacancies and changes in the electronic structure of the IGZO bulk channel and at the IGZO/SiO2 interface, which can further lead to the formation of subgap states. An attempt is made to distinguish which parameters of the FET are affected by the changes in the electronic structure of the IGZO bulk channel and at the IGZO/SiO2 interface separately.

On the Geometrically Dependent Quasi-Saturation and g(m) Reduction in Advanced DeMOS Transistors

This paper reveals an early quasi-saturation (QS) effect attributed to the geometrical parameters in shallow trench isolation-type drain-extended MOS (STI-DeMOS) transistors in advanced CMOS technologies. The quasi-saturation effect leads to serious g(m) reduction in STI-DeMOS. This paper investigates the nonlinear resistive behavior of the drain-extended region and its impact on the particular behavior of the STI-DeMOS transistor. In difference to vertical DMOS or lateral DMOS structures, STI-DeMOS exhibits three distinct regions of the drain extension. A complete understanding of the physics in these regions and their impact on the QS behavior are developed in this paper. An optimization strategy is shown for an improved g(m) device in a state-of-the-art 28-nm CMOS technology node.

Electron-hole asymmetry in the electron-phonon coupling in top-gated phosphorene transistor

Using in situ Raman scattering from phosphorene channel in an electrochemically top-gated field effect transistor, we show that phonons with A(g) symmetry depend much more strongly on concentration of electrons than that of holes, wheras phonons with B-g symmetry are insensitive to doping. With first-principles theoretical analysis, we show that the observed electon-hole asymmetry arises from the radically different constitution of its conduction and valence bands involving pi and sigma bonding states respectively, whose symmetry permits coupling with only the phonons that preserve the lattice symmetry. Thus, Raman spectroscopy is a non-invasive tool for measuring electron concentration in phosphorene-based nanoelectronic devices.