993 resultados para Voltage stabilizing circuits
Resumo:
A recently introduced power-combining scheme for a Class-E amplifier is, for the first time, experimentally validated in this paper. A small value choke of 2.2 nH was used to substitute for the massive dc-feed inductance required in the classic Class-E circuit. The power-combining amplifier presented, which operates from a 3.2-V dc supply voltage, is shown to be able to deliver a 24-dBm output power and a 9.5-dB gain, with 64% drain efficiency and 57% power-added efficiency at 2.4 GHz. The power amplifier exhibits a 350-MHz bandwidth within which a drain efficiency that is better than 60% and an output power that is higher than 22 dBm were measured. In addition, by adopting three-harmonic termination strategy, excellent second-and third-harmonic suppression levels of 50 and 46 dBc, respectively, were obtained. The complete design cycle from analysis through fabrication to characterization is explained. © 2010 IEEE.
Resumo:
Schistosomes are amongst the most important and neglected pathogens in the world, and schistosomiasis control relies almost exclusively on a single drug. The neuromuscular system of schistosomes is fertile ground for therapeutic intervention, yet the details of physiological events involved in neuromuscular function remain largely unknown. Short amidated neuropeptides, FMRFamide-like peptides (FLPs), are distributed abundantly throughout the nervous system of every flatworm examined and they produce potent myoexcitation. Our goal here was to determine the mechanism by which FLPs elicit contractions of schistosome muscle fibers. Contraction studies showed that the FLP Tyr-Ile-Arg-Phe-amide (YIRFamide) contracts the muscle fibers through a mechanism that requires Ca2+ influx through sarcolemmal voltage operated Ca2+ channels (VOCCs), as the contractions are inhibited by classical VOCC blockers nicardipine, verapamil and methoxyverapamil. Whole-cell patch-clamp experiments revealed that inward currents through VOCCs are significantly and reversibly enhanced by the application of 1 µM YIRFamide; the sustained inward currents were increased to 190% of controls and the peak currents were increased to 180%. In order to examine the biochemical link between the FLP receptor and the VOCCs, PKC inhibitors calphostin C, RO 31–8220 and chelerythrine were tested and all produced concentration dependent block of the contractions elicited by 1 µM YIRFamide. Taken together, the data show that FLPs elicit contractions by enhancing Ca2+ influx through VOCC currents using a PKC-dependent pathway.
Resumo:
We report observations of stable, localized, linelike structures in the spatially periodic pattern formed by nematic electroconvection, along which the phase of the pattern jumps by pi. With increasing electric voltage, these lines form a gridlike structure that goes over into a structure indistinguishable from the well-known grid pattern. We present theoretical arguments that suggest that the twisted cell geometry we are using is indirectly stabilizing the phase jump lines, and that the phase jump lines lattice is caused by an interaction of phase jump lines and a zig-zag instability of the surrounding pattern.
Resumo:
In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.