An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

12 W high efficiency single frequency ring laser

Single-frequency output power of 12 W at 1064 nm is demonstrated. Pumped by a fiber-coupled diode laser, the Nd:YVO4 produces 58.6% of the slope efficiency with respect to absorbed pump power, and 52.7% of the optical-optical efficiency and nearly diffraction-limited output with a beam quality parameter of M-2 approximate to 1.11. To the best of our knowledge, this is the highest slope efficiency and optical-optical efficiency in single-frequency Nd:YVO4 ring laser. The slope efficiency of the single frequency laser is close to the limit of the efficiency. [GRAPHICS] output spectrum of the single-frequency Nd:YVO4 ring laser

Ultrafast sum-frequency polarization beats in twin Markovian stochastic correlation

An analytic closed form for the second- order or fourth- order Markovian stochastic correlation of attosecond sum- frequency polarization beat ( ASPB) can be obtained in the extremely Doppler- broadened limit. The homodyne detected ASPB signal is shown to be particularly sensitive to the statistical properties of the Markovian stochastic light. fields with arbitrary bandwidth. The physical explanation for this is that the Gaussian- amplitude. field undergoes stronger intensity. fluctuations than a chaotic. field. On the other hand, the intensity ( amplitude). fluctuations of the Gaussian- amplitude. field or the chaotic. field are always much larger than the pure phase. fluctuations of the phase-diffusion field. The field correlation has weakly influence on the ASPB signal when the laser has narrow bandwidth. In contrast, when the laser has broadband linewidth, the ASPB signal shows resonant- nonresonant cross correlation, and the sensitivities of ASPB signal to three Markovian stochastic models increase as time delay is increased. A Doppler- free precision in the measurement of the energy- level sum can be achieved with an arbitrary bandwidth. The advantage of ASPB is that the ultrafast modulation period 900as can still be improved, because the energy- level interval between ground state and excited state can be widely separated.

Coherent laser control in attosecond sum-frequency polarization beats using twin noisy driving fields

Based on the phase-conjugate polarization interference between two-pathway excitations, we obtained an analytic closed form for the second-order or fourth-order Markovian stochastic correlation of the V three-level sum-frequency polarization beat (SFPB) in attosecond scale. Novel interferometric oscillatory behavior is exposed in terms of radiation-radiation, radiation-matter, and matter-matter polarization beats. The phase-coherent control of the light beams in the SFPB is subtle. When the laser has broadband linewidth, the homodyne detected SFPB signal shows resonant-nonresonant cross correlation, a drastic difference for three Markovian stochastic fields, and the autocorrelation of the SFPB exhibits hybrid radiation-matter detuning terahertz damping oscillation. As an attosecond ultrafast modulation process, it can be extended intrinsically to any sum frequency of energy levels. It has been also found that the asymmetric behaviors of the polarization beat signals due to the unbalanced controllable dispersion effects between the two arms of interferometer do not affect the overall accuracy in case using the SFPB to measure the Doppler-free energy-level sum of two excited states.

Phase and amplitude reconstruction from a single carrier-frequency interferogram without phase unwrapping

A rapid algorithm for phase and amplitude reconstruction from a single spatial-carrier interferogram is proposed by bringing a phase-shifting mechanism into reconstruction of a carrier-frequency interferogram. The algorithm reconstructs phase through directly obtaining and integrating its real-value derivatives, avoiding a phase unwrapping process. The proposed method is rapid and easy to implement and is made insensitive to the profile of the interferogram boundaries by choosing a suitable integrating path. Moreover, the algorithm can also be used to reconstruct the amplitude of the object wave expediently without retrieving the phase profile in advance. The feasibility of this algorithm is demonstrated by both numerical simulation and experiment. (c) 2008 Optical Society of America.

Harmonic Millimeter Wave Generation and Frequency Up-Conversion Using Optical Injection Locking and Brillouin Selective Sideband Amplification

Harmonic millimeter wave (mm-wave) generation and frequency up-conversion are experimentally demonstrated using optical injection locking and Brillouin selective sideband amplification (BSSA) induced by stimulated Brillouin scattering in a 10-km single-mode fiber. By using this method, we successfully generate third-harmonic mm-wave at 27 GHz (f(LO) - 9 GHz) with single sideband (SSB) modulation and up-convert the 2GHz intermediate frequency signal into the mm-wave band with single mode modulation of the SSB modes. In addition, the mm-wave carrier obtains more than 23 dB power gain due to the BSSA. The transmission experiments show that the generated mm-wave and up-converted signals indicate strong immunity against the chromatic dispersion of the fibers.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dBc/Hz@1MHz.The reference spur is -52 dBc.

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD, we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.