Human marrow mesenchymal stem Cells (MSCs) in the peplated non-adherent cell population serve as a complementary source of osteogenic cells

To obtain enough quantity of osteogenic cells is a challenge for successful cell therapy in bone defect treatment, and cell numbers were usually achieved by culturing bone marrow cells in a relatively long duration. This study reported a simple and cost effective method to enhance the number of MSCs by collecting and replating the non-adherent cell population of marrow MSCs culture. Bone marrow MSCs were isolated from 11 patients, cultured at a density of 1×105/cm2 to 1×106/cm2 in flasks. For the first three times of media change, the floating cells were centrifuged and replated in separate flasks. The total number of cells in both the primary and replating flasks were counted at day 21. Cell proliferation rate, potentials for osteogenic, chondrognenic, and adipogenic differentiation were examined in both cell types in vitro. In-vivo osteogenic potentials of the cells were also tested in mice implantation model. The results showed that MSCs derived from non-adherent cell population of marrow cell cultures have similar cell proliferation and differentiation potentials as the originally attached MSCs in vitro. When implanted with HA-TCP materials subcutaneously in SCID mice, newly formed bony tissues were found in both cell type groups with osteocalcin expression. We have obtained 36.6% (20.70%-44.97%) more MSCs in the same culture period when the non-adherent cell populations were collected. The findings confirmed that the non-adherent cell population in the bone marrow culture is a complementary source of MSCs, collecting these cells is a simple and cost-effective way to increase MSCs numbers and reduce the time required for culturing MSCs for clinical applications.

Liquid source misted chemical deposition process of three-dimensional nano-ferroelectrics with substrate heating

A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O-3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650 degrees C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Mutual impedance between two dipole antennas fed by single source

We present a new circuit-model approach which can be used to compute the mutual impedance between two dipoles fed at the same feed point. The validity of the method is confirmed by comparison with mutual impedance values obtained when the dipoles are individually excited and orientated at angles between 0degrees and 90degrees. (C) 2004 Wiley Periodicals, Inc.

MISEP method for postnonlinear blind source separation

In this letter, a standard postnonlinear blind source separation algorithm is proposed, based on the MISEP method, which is widely used in linear and nonlinear independent component analysis. To best suit a wide class of postnonlinear mixtures, we adapt the MISEP method to incorporate a priori information of the mixtures. In particular, a group of three-layered perceptrons and a linear network are used as the unmixing system to separate sources in the postnonlinear mixtures, and another group of three-layered perceptron is used as the auxiliary network. The learning algorithm for the unmixing system is then obtained by maximizing the output entropy of the auxiliary network. The proposed method is applied to postnonlinear blind source separation of both simulation signals and real speech signals, and the experimental results demonstrate its effectiveness and efficiency in comparison with existing methods.

Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.