Dinámica del carbono en sistemas agrícolas bajo siembra directa : nuevas evidencias obtenidas mediante el uso de 13 C sobre la importancia de las raíces, la calidad de los residuos y el laboreo

El carbono orgánico del suelo (COS) es uno de los principales determinantes de la productividad de los ecosistemas, afectando la fertilidad del suelo y su capacidad de secuestrar CO2. La agricultura es uno de los principales cambios de uso del suelo que afecta significativamente el COS. En esta tesis se examinan, mediante experimentos de campo y usando al 13C como trazador isotópico, tres aspectos de la dinámica de C en sistemas agrícolas: 1) la importancia de las raíces en la formación de COS, 2) los efectos de la cantidad y calidad de los residuos sobre la tasa de descomposición y humificación del COS y 3) la dinámica del COS en sistemas de agricultura continua iniciados sobre pastizales naturales nunca laboreados. Los resultados obtenidos muestran que 1) en cultivos de soja y maíz, la formación de COS se deriva principalmente de la biomasa subterránea y en menor medida de los residuos aéreos, al menos en la fracción de la materia orgánica particulada (MOP). También, se observó 2) que el agregado de residuos de maíz con alta relación C:N aumentó la tasa de descomposición de la MOAM (materia orgánica asociada a los minerales) cuando se la compara con el agregado de residuos de soja (baja relación C:N), efecto conocido como priming. Sin embargo, también existió una mayor formación de materia orgánica bajo cultivos de maíz, y por ende se conservaron las reservas de COS, pero su ciclado fue más rápido. Finalmente, 3) los cultivos en sistemas de siembra directa establecidos sobre suelos nunca laboreados presentaron niveles de COS similares a los de los pastizales naturales remplazados. Estos resultados cuestionan parte de nuestro conocimiento sobre los sistemas agrícolas bajo siembra directa, aportando nuevas evidencias experimentales y destacando el uso de marcadores isotópicos de 13C para comprender el flujo de C en los agroecosistemas.

A life cycle model for product-service systems design

Western manufacturing companies are developing innovative ways of delivering value that competes with the low cost paradigm. One such strategy is to deliver not only products, but systems that are closely aligned with the customer value proposition. These systems are comprised of integrated products and services, and are referred to as Product-Service Systems (PSS). A key challenge in PSS is supporting the design activity. In one sense, PSS design is a further extension of concurrent engineering that requires front-end input from the additional downstream sources of product service and maintenance. However, simply developing products and service packages is not sufficient: the new design challenge is the integrated system. This paper describes the development of a PSS data structure that can support this integrated design activity. The data structure is implemented in a knowledge base using the Protégé knowledge base editor.

Analysis and Synthesis of pHEMT Class-E Amplifiers with Shunt Inductor including ON-State Active-Device Resistance Effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers

Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50 duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100 but power output capability is less than that the 50 duty ratio case would permit. To facilitate comparison between 50 (optimal) and non-50 (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50 suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. © The Institution of Engineering and Technology 2007.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Synthesis of a neodymium-quinolate complex for near-infrared electroluminescence applications

A structurally pure, near-infrared emissive Nd-(5,7-dichloro-8-hydroxyquinoline)4 tetrakis complex has been synthesized. When incorporated as a dopant in the blue emissive, hole conducting polymer poly(N-vinylcarbazole), PVK, sensitized neodymium ion emission was observed following photo-excitation of the polymer host. OLED devices were fabricated by spin-casting layers of the doped polymer onto glass/indium tin oxide (ITO)/3,4-polyethylene-dioxythiophene-polystyrene sulfonate (PEDOT) substrates. An external quantum efficiency of 1 x 10(-3)% and a near-infrared irradiance of 2.0 nW/mm(2) at 25 mA/mm(2) and 20 V was achieved using glass/ITO/PEDOT/ PVK:Nd-(5,7-dichloro-8-hydroxyquinoline)(4)/Ca/Al devices. (C) 2007 Elsevier B.V. All rights reserved.

Near infrared electroluminescence from neodymium complex-doped polymer light emitting diodes

Organic light emitting diode devices employing organometallic Nd(9-hydroxyphenalen-1-one)(3) complexes as near infrared emissive dopants dispersed within poly(N-vinylcarbazole) (PVK) host matrices have been fabricated by spin-casting layers of the doped polymer onto glass/indium tin oxide (ITO)/3,4-polyethylene-dioxythiophene-polystyrene sulfonate (PEDOT) substrates. Room temperature electroluminescence, centered at similar to 1065 nm. was observed from devices top contacted by evaporated aluminum or calcium metal cathodes and was assigned to transitions between the F-4(3/2) -> I-4(11/2) levels of the Nd3+ ions. In particular, a near infrared irradiance of 8.5 nW/mm(2) and an external quantum efficiency of 0.007% was achieved using glass/ITO/PEDOT/PVK:Nd(9-hydroxyphenalen-1-one)(3)/Ca/Al devices. (c) 2005 Elsevier B.V. All rights reserved.

Narrow bandwidth red electroluminescence from solution-processed lanthanide-doped polymer thin films

Narrow bandwidth red electroluminescence from OLED devices fabricated using a simple solution-based approach is demonstrated. A spin-casting method is employed to fabricate organic light emitting diode (OLED) devices comprising a poly(N-vinylcarbazole) (PVK) host matrix doped with a europium beta-diketonate complex, Eu(dbM)(3)(Phen) (dibenzoylmethanate, dbm; 1,10-phenanthroline, Phen) on glass/ indium tin oxide (ITO)/3,4-polyethylene-dioxythiophene-polystyrene sulfonate (PEDOT) substrates. Saturated red europium ion emission, based on the (5)Do ->F-7(2) transition, is centered at a wavelength of 612 nm with a full width at half maximum of 3.5 rim. A maximum external quantum efficiency of 6.3 x 10(-2) cd/A (3.1 X 10(-2)%) and a maximum luminance of 130 cd/M-2 at 400 mA/cm(2) and 25 V is measured for ITO/PEDOT/PVK:Eu(dbM)3(Phen)/Ca/Al devices. This measured output luminance is comparable to that of devices fabricated using more sophisticated small molecule evaporation techniques. (c) 2005 Elsevier B.V All rights reserved.

Non Classical Design in MOSFETs for Improving OTA gain-bandwidth trade off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .

Design, Manufacture and Performance of Germanium Bipolar Transistors

Germanium NPN bipolar transistors have been manufactured using phosphorus and boron ion implantation processes. Implantation and subsequent activation processes have been investigated for both dopants. Full activation of phosphorus implants has been achieved with RTA schedules at 535?C without significant junction diffusion. However, boron implant activation was limited and diffusion from a polysilicon source was not practical for base contact formation. Transistors with good output characteristics were achieved with an Early voltage of 55V and common emitter current gain of 30. Both Silvaco process and device simulation tools have been successfully adapted to model the Ge BJT(bipolar junction transistor) performance.

Analysis of alteration of p75NTR processing and signalling by PS2 mutation and gamma-secretase inhibition

The presenilins (PSs) were identified as causative genes in cases of early-onset familial Alzheimer's disease (AD) and current evidence indicates that PSs are part of the gamma-secretase complex responsible for proteolytic processing of type I membrane proteins. p75NTR, a common neurotrophin receptor, was shown to be subject to gamma-secretase processing. However, it is not clear if the p75NTR downstream signal is altered in response to gamma-secretase cleavage, and further there is a possibility that AD-related PS mutations may affect this cleavage, resulting in pathogenic alterations in signal transduction. In this study, we confirmed that p75NTR downstream signalling is altered by PS2 mutation or gamma-secretase inhibition in SHSY-5Y cells. The activity of the small GTPase RhoA is strongly affected by these treatments. This study demonstrates that gamma-secretase and PS2 play an important role in regulating neurotrophin signal transduction and either mutation of PS2 or inhibition of gamma-secretase disturbs this function.