Low Complexity Intra Mode Selection for Efficient Distributed Video Coding

Motion compensated frame interpolation (MCFI) is one of the most efficient solutions to generate side information (SI) in the context of distributed video coding. However, it creates SI with rather significant motion compensated errors for some frame regions while rather small for some other regions depending on the video content. In this paper, a low complexity Infra mode selection algorithm is proposed to select the most 'critical' blocks in the WZ frame and help the decoder with some reliable data for those blocks. For each block, the novel coding mode selection algorithm estimates the encoding rate for the Intra based and WZ coding modes and determines the best coding mode while maintaining a low encoder complexity. The proposed solution is evaluated in terms of rate-distortion performance with improvements up to 1.2 dB regarding a WZ coding mode only solution.

Phototransistor with nanocrystalline Si/amorphous Si bilayer channel

We report a field-effect phototransistor with a channel comprising a thin nanocrystalline silicon transport layer and a thicker hydrogenated amorphous silicon absorption layer. The semiconductor and dielectric layers were deposited by radio-frequency plasma enhanced chemical vapor deposition. The phototransistor with channel length of 24 microns and photosensitive area of 1.4 mm(2) shows an off-current of about 1 pA, and high photoconductive gain in the subthreshold region. Measurements of the quantum efficiency at different incident light intensities and biasing conditions, along with spectral-response characteristics, and threshold voltage stability characterization demonstrate the feasibility of the phototransistor for low light level detection.

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

Repetitive Solid State Pulse Modulator Based on a DC Voltage Multiplier

A newly developed solid-state repetitive high-voltage (HV) pulse modulator topology created from the mature concept of the d.c. voltage multiplier (VM) is described. The proposed circuit is based in a voltage multiplier type circuit, where a number of d.c. capacitors share a common connection with different voltage rating in each one. Hence, besides the standard VM rectifier and coupling diodes, two solid-state on/off switches are used, in each stage, to switch from the typical charging VM mode to a pulse mode with the d.c. capacitors connected in series with the load. Due to the on/off semiconductor configuration, in half-bridge structures, the maximum voltage blocked by each one is the d.c. capacitor voltage in each stage. A 2 kV prototype is described and the results are compared with PSPICE simulations.

Poverty levels and children's health status: study of risk factors in an urban population of low socioeconomic level

To test the hypothesis that the low socioeconomic population living is shanty towns in Porto Alegre presents different levels of poverty which are reflected on its health status, a cross-sectional study was designed involving 477 families living in Vila Grande Cruzeiro, Porto Alegre, Brazil. The poverty level of the families was measured by using an instrument specifically designed for poor urban populations. Children from families living in extreme poverty (poorest quartile) were found to have higher infant mortality rate, lower birth weights, more hospitalizations, and higher malnutrition rates, in addition to belonging to more numerous families. Thus, the shanty town population of Porto Alegre is not homogeneous, and priority should be given to the more vulnerable subgroups.

Indoor school environment: easy and low cost to assess inorganic pollutants

Total particulate matter (TPM) was passively collected inside two classrooms of each of five elementary schools in Lisbon, Portugal. TPM was collected in polycarbonate filters with a 47 mm diameter, placed inside of uncovered plastic petri dishes. The sampling period was from 19 May to 22 June 2009 (35 days exposure) and the collected TPM masses varied between 0.2 mg and 0.8 mg. The major elements were Ca, Fe, Na, K, and Zn at μg level, while others were at ng level. Pearson′s correlation coefficients above 0.75 (a high degree of correlation) were found between several elements. Soil-related, traffic soil re-suspension and anthropogenic emission sources could be identified. Blackboard chalk was also identified through Ca large presence. Some of the determined chemical elements are potential carcinogenic. Quality control of the results showed good agreement as confirmed by the application of u-score test.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

RF Receiver Front End for 28.5 GHz Applications on a 70 GHz F-T SiGe BiCMOS Process

This article presents the design and test of a receiver front end aimed at LMDS applications at 28.5 GHz. It presents a system-level design after which the receiver was designed. The receiver comprises an LNA, quadrature mixer and quadrature local oscillator. Experimental results at 24 GHz center frequency show a conversion voltage gain of 15 dB and conversion noise figure of 14 5 dB. The receiver operates from a 2 5 V power supply with a total current consumption of 31 mA.

Bias dependent photocurrent collection in p-i-n a-Si : EVSiC : H heterojunction

A series of large area single layers and heterojunction cells in the assembly glass/ZnO:Al/p (SixC1-x:H)/i (Si:H)/n (SixC1-x:H)/Al (0 low temperature. Junction properties, carrier transport and photogeneration are investigated from dark and illuminated current-voltage and capacitance-voltage characteristics. For the heterojunction cells S-shaped J-V characteristics under different illumination conditions are observed leading to poor fill factors. High serial resistances around 10(5)Ohm are also measured Simulated results confirm the experimental findings suggesting that the transport in dark depends almost exclusively on field-aided drift while under illumination it is dependent mainly on minority carriers the diffusion.

Bias-dependent photocurrent collection in p-i-n a-Si : H/SiC : H heterojunction

A series of large area single layers and glass/ZnO:AVp(SixC1-x:H)/i(Si:H)/n(SixC1-x:H)/AI (0 < x < 1) heterojunction cells were produced by plasma-enhanced chemical vapour deposition (PE-CVD) at low temperature. Junction properties, carrier transport and photogeneration are investigated from dark and illuminated current-voltage (J-V) and capacitance-voltage (C-V) characteristics. For the heterojunction cells atypical J-V characteristics under different illumination conditions are observed leading to poor fill factors. High series resistances around 106 Q are also measured. These experimental results were used as a basis for the numerical simulation of the energy band diagram, and the electrical field distribution of the structures. Further comparison with the sensor performance gave satisfactory agreement. Results show that the conduction band offset is the most limiting parameter for the optimal collection of the photogenerated carriers. As the optical gap increases and the conductivity of the doped layers decreases, the transport mechanism changes from a drift to a diffusion-limited process.

Image and color recognition using amorphous silicon p-i-n photodiodes

Large area hydrogenated amorphous silicon single and stacked p-i-n structures with low conductivity doped layers are proposed as monochrome and color image sensors. The layers of the structures are based on amorphous silicon alloys (a-Si(x)C(1-x):H). The current-voltage characteristics and the spectral sensitivity under different bias conditions are analyzed. The output characteristics are evaluated under different read-out voltages and scanner wavelengths. To extract information on image shape, intensity and color, a modulated light beam scans the sensor active area at three appropriate bias voltages and the photoresponse in each scanning position ("sub-pixel") is recorded. The investigation of the sensor output under different scanner wavelengths and varying electrical bias reveals that the response can be tuned, thus enabling color separation. The operation of the sensor is exemplified and supported by a numerical simulation.

ITO/SiOx/Si optical sensor with internal gain

A visible/near-infrared optical sensor based on an ITO/SiOx/n-Si structure with internal gain is presented. This surface-barrier structure was fabricated by a low-temperature processing technique. The interface properties and carder transport were investigated from dark current-voltage and capacitance-voltage characteristics. Examination of the multiplication properties was performed under different light excitation and reverse bias conditions. The spectral and pulse response characteristics are analysed. The current amplification mechanism is interpreted by the control of electron current by the space charge of photogenerated holes near the SiOx/Si interface. The optical sensor output characteristics and some possible device applications are presented.

Stacked pin Devices for Imaging Applications

In this paper we present results on the optimization of device architectures for colour and imaging applications, using a device with a TCO/pinpi'n/TCO configuration. The effect of the applied voltage on the color selectivity is discussed. Results show that the spectral response curves demonstrate rather good separation between the red, green and blue basic colors. Combining the information obtained under positive and negative applied bias a colour image is acquired without colour filters or pixel architecture. A low level image processing algorithm is used for the colour image reconstruction.

Projecto de um regulador linear de tensão: LDO

Os reguladores de tensão LDO são utilizados intensivamente na actual indústria de electrónica, são uma parte essencial de um bloco de gestão de potência para um SoC. O aumento de produtos portáteis alimentados por baterias levou ao crescimento de soluções totalmente integradas, o que degrada o rendimento dos blocos analógicos que o constituem face às perturbações introduzidas na alimentação. Desta forma, surge a necessidade de procurar soluções cada vez mais optimizadas, impondo assim novas soluções, e/ou melhoramentos dos circuitos de gestão de potência, tendo como objectivo final o aumento do desempenho e da autonomia dos dispositivos electrónicos. Normalmente este tipo de reguladores tem a corrente de saída limitada, devido a problemas de estabilidade associados. Numa tentativa de evitar a instabilidade para as correntes de carga definidas e aumentar o PSRR do mesmo, é apresentado um método de implementação que tem como objectivo melhorar estas características, em que se pretende aumentar o rendimento e melhorar a resposta à variação da carga. No entanto, a técnica apresentada utiliza polarização adaptativa do estágio de potência, o que implica um aumento da corrente de consumo. O regulador LDO foi implementado na tecnologia CMOS UMC 0.18μm e ocupa uma área inferior a 0,2mm2. Os resultados da simulação mostram que o mesmo suporta uma transição de corrente 10μA para 100mA, com uma queda de tensão entre a tensão de alimentação e a tensão de saída inferior a 200mV. A estabilidade é assegurada para todas as correntes de carga. O tempo de estabelecimento é inferior a 6μs e as variações da tensão de saída relativamente a seu valor nominal são inferiores a 5mV. A corrente de consumo varia entre os 140μA até 200μA, o que permite atingir as especificações proposta para um PSRR de 40dB@10kHz.

Risk factors for the increasing trend in low birth weight among live births born by vaginal delivery, Brazil

OBJECTIVE: To identify risk factors for low birth weight (LBW) among live births by vaginal delivery and to determine if the disappearance of the association between LBW and socioeconomic factors was due to confounding by cesarean section. METHODS: Data were obtained from two population-based cohorts of singleton live births in Ribeirão Preto, Southeastern Brazil. The first one comprised 4,698 newborns from June 1978 to May 1979 and the second included 1,399 infants born from May to August 1994. The risks for LBW were tested in a logistic model, including the interaction of the year of survey and all independent variables under analysis. RESULTS: The incidence of LBW among vaginal deliveries increased from 7.8% in 1978--79 to 10% in 1994. The risk was higher for: female or preterm infants; newborns of non-cohabiting mothers; newborns whose mothers had fewer prenatal visits or few years of education; first-born infants; and those who had smoking mothers. The interaction of the year of survey with gestational age indicated that the risk of LBW among preterm infants fell from 17.75 to 8.71 in 15 years. The mean birth weight decreased more significantly among newborns from qualified families, who also had the highest increase in preterm birth and non-cohabitation. CONCLUSIONS: LBW among vaginal deliveries increased mainly due to a rise in the proportion of preterm births and non-cohabiting mothers. The association between cesarean section and LBW tended to cover up socioeconomic differences in the likelihood of LBW. When vaginal deliveries were analyzed independently, these socioeconomic differences come up again.