991 resultados para Vascular closure devices
Resumo:
Bioavailable water concentrations of polycyclic aromatic hydrocarbons (PAH), polychlorinated biphenyls (PCB) and organochlorine pesticides (OCP) were measured in the water column from Three Gorges Reservoir (TGR) collected in May 2008 using semipermeable membrane devices (SPMDs). The sampling sites spanned the whole reservoir from the upstream Chongqing to the great dam covering more than 600 km long distance with water flow velocities ranging from <0.05 to 1.5 m s(-1). This is the first experience of SPMD application in the biggest reservoir in the world. The results of water sampling rates based on performance reference compounds (PRC) were tested to be significantly correlated with water flow velocities in the big river. Results of back-calculated aqueous concentrations based on PRC showed obvious regional variations of PAH, PCB and OCP levels in the reservoir. Total PAH ranged from 13.8 to 97.2 ng L-1, with the higher concentrations occurring in the region of upstream and near the dam. Phenanthrene, fluoranthene, pyrene and chrysene were the predominant PAH compounds in TGR water. Total PCB ranged from 0.08 to 0.51 ng L-1, with the highest one occurring in the region near the dam. PCB 28, 52, 101, 138, 153, 180, 118 were the most abundant PCB congeners in the water. The total OCP ranged from 2.33 to 3.60 ng L-1 and the levels showed homogenous distribution in the whole reservoir. HCH, DDT and HCB, PeCB were the major compounds of OCP fingerprints. Based on water quality criteria, the TGR water could be designated as being polluted by HCB and PAH. Data on PAH, PCB and OCP concentrations found in this survey can be used as reference levels for future POP monitoring programmes in TGR. (C) 2009 Elsevier Ltd. All rights reserved.
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Liquid crystal on silicon (LCOS) is one of the most exciting technologies, combining the optical modulation characteristics of liquid crystals with the power and compactness of a silicon backplane. The objective of our work is to improve cell assembly and inspection methods by introducing new equipment for automated assembly and by using an optical inspection microscope. A Suss-MicroTec Universal device bonder is used for precision assembly and device packaging and an Olympus BX51 high resolution microscope is employed for device inspection. © 2009 Optical Society of America.
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Benthic macroinvertebrates were assessed monthly in Xiangxi Bay of the Three Gorges Reservoir for two years after the initial closure of the dam. Mean total density of macroinvertebrates varied from 275 ind./m(2) during the first year to 5,094 ind./m(2) during the second year, and the community of 50 taxa was overwhelmingly dominated by oligochaetes and chironomids (44 and 48% of the total taxa, respectively). As sediment accumulated in the substrate of the bay, the species composition changed dramatically, with oligochaetes comprising 91.3-99.3% of the total abundance during the second year. The dominant oligochaetes were Limnodrilus hoffmeisteri and Nais inflata. The chironomids Procladius sp., and Polypedilum scalaenum group sp. were similarly abundant in both years.
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A method to reduce crosstalk is proposed for holographic wavelength selective switches (WSSs) using a customized merit function. A reduction in crosstalk >8 dB is measured when multicasting with a phase-only LCOS device. © OSA 2014.
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Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.
Resumo:
To form low-resistance Ohmic contact to p-type GaN, InGaN/GaN multiple quantum well light emitting diode wafers are treated with boiled aqua regia prior to Ni/Au (5 nm/5 nm) film deposition. The surface morphology of wafers and the current-voltage characteristics of fabricated light emitting diode devices are investigated. It is shown that surface treatment with boiled aqua regia could effectively remove oxide from the surface of the p-GaN layer, and reveal defect-pits whose density is almost the same as the screw dislocation density estimated by x-ray rocking curve measurement. It suggests that the metal atoms of the Ni/Au transparent electrode of light emitting diode devices may diffuse into the p-GaN layer along threading dislocation lines and form additional leakage current channels. Therefore, the surface treatment time with boiled aqua regia should not be too long so as to avoid the increase of threading dislocation-induced leakage current and the degradation of electrical properties of light emitting diodes
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Spatially-resolved electroluminescence (EL) images from solar cells contain information of local current distribution. By theoretical analysis of the EL intensity distribution, the current density distribution under a certain current bias and the sheet resistance can be obtained quantitatively. Two-dimensional numerical simulation of the current density distribution is employed to a GaInP cell, which agrees very well with the experimental results. A reciprocity theorem for current spreading is found and used to interpret the EL images from the viewpoint of current extraction. The optimization of front electrodes is discussed based on the results. (C) 2010 American Institute of Physics. [doi:10.1063/1.3431390]
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This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.
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A novel and simple way to prepare high-reflectivity bottom mirrors for Si-based micro-cavity devices is reported. The bottom mirror was deposited in the hole, which was etched from the backside of the sample by ethylenediamine-pyrocatechol-water solution with the buried Sio, layer in the silicon-on-insulator substrate as the etching-stop layer. The high-reflectivity of the bottom mirror deposited in the hole and the narrow hill width at half maximum of the cavity formed by this method both indicate the successful preparation of the bottom mirror for Si-based micro-cavity devices.
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A nondestructive selection technique for predicting ionizing radiation effects of commercial metal-oxide-semiconductor (MOS) devices has been put forward. The basic principle and application details of this technique have been discussed. Practical application for the 54HC04 and 54HC08 circuits has shown that the predicted radiation-sensitive parameters such as threshold voltage, static power supply current and radiation failure total dose are consistent with the experimental results obtained only by measuring original electrical parameters. It is important and necessary to choose suitable information parameters. This novel technique can be used for initial radiation selection of some commercial MOS devices.
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SOI (silicon-on-insulator) is a new material with a lot of important performances such as large index difference, low transmission loss. Fabrication processes for SOI based optoelectronic devices are compatible with conventional IC processes. Having the potential of OEIC monolithic integration, SOI based optoelectronic devices have shown many good characteristics and become more and more attractive recently. In this paper, the recent progresses of SOI waveguide devices in our research group are presented. By highly effective numerical simulation, the single mode conditions for SOI rib waveguides with rectangular and trapezoidal cross-section were accurately investigated. Using both chemical anisotropic wet etching and plasma dry etching techniques, SOI single mode rib waveguide, MMI coupler, VOA (variable optical attenuator), 2X2 thermal-optical switch were successfully designed and fabricated. Based on these, 4X4 and 8X8 SOI optical waveguide integrated switch matrixes are demonstrated for the first time.
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This paper reviews our work on controlled growth of self-assembled semiconductor nanostructures, and their application in light-emission devices. High-power, long-life quantum dots (QD) lasers emitting at similar to 1 mu m, red-emitting QD lasers, and long-wavelength QD lasers on GaAs substrates have successfully been achieved by optimizing the growth conditions of QDs.
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A new type of photovoltaic system with higher generation power density has been studied in detail. The feature of the proposed system is a V-shaped structure with two polycrystalline solar cells. Compared to solar cells in a conventional approach, the V-shaped structure enhances external quantum efficiency and leads to an increase of 24% in power conversion efficiency.
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Self-assembled quantum dots and wires were obtained in the InxGa1-xAs/GaAs and InAs/In0.52Al0.48As/lnP systems, respectively, using molecular beam epitaxy (MBE). Uniformity in the distribution, density, and spatial ordering of the nanostructures can be controlled to some extent by adjusting and optimizing the MBE growth parameters. Laser devices and superluminescent diodes were fabricated with InAs/GaAs self-assembled quantum dots as the active region.
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This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.