An Inter-digital Capacitive Electrode Modified as a Pressure Sensor

Inter-digital capacitive electrodes working as electric field sensors have been developed for touch panel applications. Evaluation circuits to convert variations in electric fields in such sensors into computer compatible data are commercially available. We report development of an Interdigital capacitive electrode working as a sensitive pressure sensor in the range 0-120 kPa. Essentially it is a touch/proximity sensor converted into a pressure sensor with a suitable elastomer buffer medium acting as the pressure transmitter. The performance of the sensor has been evaluated and reported. Such sensors can be made very economical in comparison to existing pressure sensors. Moreover, they are very convenient to be fabricated into sensor arrays involving a number of sensors for distributed pressure sensing applications such as in biomedical systems.

Development and Analysis of a Compact Dual-Band Coplanar Antenna

The coplanar wave guide is an attractive device in microwave integrated circuits due to its uniplanar nature, ease of fabrication and low production cost. Several attempts are already done to explore the radiating modes in coplanar wave guide transmission lines. Usually coplanar wave guides are excited by an SMA connector with its centre conductor connected to the exact middle of the centre strip and the outer ground conductor to the two ground strips. The mode excited on it is purely a bound mode. The E-field distribution in the two slots are out of phase and there for cancels at the far field. This thesis addresses an attempt to excite an in phase E-field distribution in the two slots of the co planar wave guide by employing a feed asymmetry, in order to get radiation from the two large slot discontinuities of the coplanar waveguide. The omni directional distribution of the radiating energy can be achieved by widening the centre strip.The first part of the thesis deals with the investigations on the resonance phenomena of conventional coplanar waveguides at higher frequency bands. Then an offset fed open circuited coplanar waveguide supporting resonance/radiation phenomena is analyzed. Finally, a novel compact co planar antenna geometry with dual band characteristics, suitable for mobile terminal applications is designed and characterized using the inferences from the above study.

Ultra-wideband slot antenna for wireless USB dongle applications

An ultra-wideband (UWB) printed slot antenna, suitable for integration with the printed circuit board (PCB) of a wireless universal serial-bus (WUSB) dongle is presented. The design comprises a near-rectangular slot fed by a coplanar waveguide printed on a PCB of width 20 mm. The proposed design has a large bandwidth covering the 3.1-10.6 GHz UWB band, unaffected by the ground length, and omnidirectional radiation patterns. A linear phase response throughout the band further confirms its suitability for high-speed wireless connectivity.

C-shaped slot loaded reconfigurable microstrip antenna

A new electronically reconfigurable dual frequency microstrip patch antenna with highly simplified varactor tuning circuitry is presented. The proposed design allows relatively independent selection of the two operating frequencies. Tuning ranges of 7.1 and 4.1% are realised for the two resonant frequencies without the use of any matching circuits.

Regulation of GABA(A) and glutamate receptor expression, synaptic facilitation and long-term potentiation in the hippocampus of prion mutant mice

Background: Prionopathies are characterized by spongiform brain degeneration, myoclonia, dementia, and periodic electroencephalographic (EEG) disturbances. The hallmark of prioniopathies is the presence of an abnormal conformational isoform (PrP(sc)) of the natural cellular prion protein (PrP(c)) encoded by the Prnp gene. Although several roles have been attributed to PrP(c), its putative functions in neuronal excitability are unknown. Although early studies of the behavior of Prnp knockout mice described minor changes, later studies report altered behavior. To date, most functional PrP(c) studies on synaptic plasticity have been performed in vitro. To our knowledge, only one electrophysiological study has been performed in vivo in anesthetized mice, by Curtis and coworkers. They reported no significant differences in paired-pulse facilitation or LTP in the CA1 region after Schaffer collateral/commissural pathway stimulation. Principal Findings: Here we explore the role of PrP(c) expression in neurotransmission and neural excitability using wild-type, Prnp -/- and PrP(c)-overexpressing mice (Tg20 strain). By correlating histopathology with electrophysiology in living behaving mice, we demonstrate that both Prnp -/- mice but, more relevantly Tg20 mice show increased susceptibility to KA, leading to significant cell death in the hippocampus. This finding correlates with enhanced synaptic facilitation in paired-pulse experiments and hippocampal LTP in living behaving mutant mice. Gene expression profiling using Illumina microarrays and Ingenuity pathways analysis showed that 129 genes involved in canonical pathways such as Ubiquitination or Neurotransmission were co-regulated in Prnp -/- and Tg20 mice. Lastly, RT-qPCR of neurotransmission-related genes indicated that subunits of GABA(A) and AMPA-kainate receptors are co-regulated in both Prnp -/- and Tg20 mice. Conclusions/Significance: Present results demonstrate that PrP(c) is necessary for the proper homeostatic functioning of hippocampal circuits, because of its relationships with GABA(A) and AMPA-Kainate neurotransmission. New PrP(c) functions have recently been described, which point to PrP(c) as a target for putative therapies in Alzheimer's disease. However, our results indicate that a "gain of function" strategy in Alzheimer's disease, or a "loss of function" in prionopathies, may impair PrP(c) function, with devastating effects. In conclusion, we believe that present data should be taken into account in the development of future therapies.

Energy Management in Wireless Sensor Networks: A Crosslayer,Channel Adaptive Approach Towards Performance Optimization

The proliferation of wireless sensor networks in a large spectrum of applications had been spurered by the rapid advances in MEMS(micro-electro mechanical systems )based sensor technology coupled with low power,Low cost digital signal processors and radio frequency circuits.A sensor network is composed of thousands of low cost and portable devices bearing large sensing computing and wireless communication capabilities. This large collection of tiny sensors can form a robust data computing and communication distributed system for automated information gathering and distributed sensing.The main attractive feature is that such a sensor network can be deployed in remote areas.Since the sensor node is battery powered,all the sensor nodes should collaborate together to form a fault tolerant network so as toprovide an efficient utilization of precious network resources like wireless channel,memory and battery capacity.The most crucial constraint is the energy consumption which has become the prime challenge for the design of long lived sensor nodes.

Studies on the universal parameters and onset of chaos in dissipative systems

It has become clear over the last few years that many deterministic dynamical systems described by simple but nonlinear equations with only a few variables can behave in an irregular or random fashion. This phenomenon, commonly called deterministic chaos, is essentially due to the fact that we cannot deal with infinitely precise numbers. In these systems trajectories emerging from nearby initial conditions diverge exponentially as time evolves)and therefore)any small error in the initial measurement spreads with time considerably, leading to unpredictable and chaotic behaviour The thesis work is mainly centered on the asymptotic behaviour of nonlinear and nonintegrable dissipative dynamical systems. It is found that completely deterministic nonlinear differential equations describing such systems can exhibit random or chaotic behaviour. Theoretical studies on this chaotic behaviour can enhance our understanding of various phenomena such as turbulence, nonlinear electronic circuits, erratic behaviour of heart and brain, fundamental molecular reactions involving DNA, meteorological phenomena, fluctuations in the cost of materials and so on. Chaos is studied mainly under two different approaches - the nature of the onset of chaos and the statistical description of the chaotic state.

Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters

In a sigma-delta analog to digital (A/D) As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs are The first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.

Fault Tolerant Error Coding and Detection using Reversible Gates

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Evaluation of the Power Consumption of Routing Protocols for Wireless Sensor Networks

Sensor networks are one of the fastest growing areas in broad of a packet is in transit at any one time. In GBR, each node in the network can look at itsneighbors wireless ad hoc networking (? Eld. A sensor node, typically'hop count (depth) and use this to decide which node to forward contains signal-processing circuits, micro-controllers and a the packet on to. If the nodes' power level drops below a wireless transmitter/receiver antenna. Energy saving is one certain level it will increase the depth to discourage trafiE of the critical issue for sensor networks since most sensors are equipped with non-rechargeable batteries that have limitedlifetime. Routing schemes are used to transfer data collectedby sensor nodes to base stations. In the literature many routing protocols for wireless sensor networks are suggested. In this work, four routing protocols for wireless sensor networks viz Flooding, Gossiping, GBR and LEACH have been simulated using TinyOS and their power consumption is studied using PowerTOSSIM. A realization of these protocols has beencarried out using Mica2 Motes.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Evaluation of the Power Consumption of Routing Protocols for Wireless Sensor Networks

Sensor networks are one of the fastest growing areas in broad of a packet is in transit at any one time. In GBR, each node in the network can look at itsneighbors wireless ad hoc networking (? Eld. A sensor node, typically'hop count (depth) and use this to decide which node to forward contains signal-processing circuits, micro-controllers and a the packet on to. If the nodes' power level drops below a wireless transmitter/receiver antenna. Energy saving is one certain level it will increase the depth to discourage trafiE of the critical issue forfor sensor networks since most sensors are equipped with non-rechargeable batteries that have limited lifetime.