Fabrication of 4 x 4 tapered MMI coupler with large cross section

MMI coupler with large cross section has low coupling loss between the device and fiber. However, large chip area is required. Recently proposed N x N tapered MMI coupler shows a substantial reduction in device geometry. No such kind of devices with N > 2 has yet been realized up to now. The authors have demonstrated a 4 x 4 parabolically tapered MMI coupler with large cross section that can match the SM fiber in silicon-on-insulator (SOI) technology. The device exhibits a minimum uniformity of 0.36 dB and excess loss of 3.7 dB, It represents a key component for realization of MMI-based silicon integrated optical circuit technology.

Effective method for evaluation of semiconductor laser quality

The measurements of one hundred 1.3 mu m planar buried crescent (PBC) structure InGaAsP/InP lasers demonstrate that parameters given by the electrical derivative of varied temperature and the variation of the parameters with temperature can be used to appraise the quality and reliability of semiconductor lasers effectual. By measurement of electrical derivative curves one can evaluate the quality of epitaxial wafer and chip, find the problems in the material and the technology, offer the useful information on increasing the quality and improving the technology of devices. (C) 2000 Elsevier Science Ltd. All rights reserved.

High efficiency fiber to waveguide optical coupler in silicon-on-insulator-based slot waveguides - art. no. 68310R

We propose a novel optical fiber-to-waveguide coupler for integrated optical circuits. The proper materials and structural parameters of the coupler, which is based on a slot waveguide, are carefully analyzed using a full-vectorial three dimensional mode solver. Because the effective refractive index of the mode in a silicon-on-insulator-based slot waveguide can be extremely close to that of the fiber, a highly efficient fiber-to-waveguide coupling application can be realized. For a TE-like mode, the calculated minimum mismatch loss is about 1.8dB at 1550nm, and the mode conversion loss can be less than 0.5dB. The discussion of the present state-of-the-art is also involved. The proposed coupler can be used in chip-to-chip communication.

Optimized design on high-power GaN-based Micro-LEDs - art. no. 684108

The structure of micro-LEDs was optimized designed. Optical, electrical and thermal characteristics of micro-LEDs were improved. The optimized design make micro-LEDs suitable for high-power device. The light extraction efficiency of micro-LEDs was analyzed by the means of ray tracing. The results shows that increasing the inclination angle of sidewall and height of mesa, and reducing the absorption of p and n electrode can enhance the light extraction efficiency of micro-LEDs. Furthermore, the total light output power can be boosted by increasing the density of micro-structures on the device. The high-power flip-chip micro-LEDs were fabricated, which has higher quantum efficiency than conventional BALED's. When the number of microstructure in micro-LEDs was increased by 57%, the light output power was enhanced 24%. Light output power is 82.88mW at the current of 350mA and saturation current is up to 800mA, all of these are better than BALED which was fabricated in the same epitaxial wafer. The IN characteristics of micro-LEDs are almost identical to BALED.

The effects of sapphire substrates processes to the LED efficiency - art. no. 68410M

We investigate the relation between the thickness of sapphire substrates and the extraction efficiency of LED. The increasing about 5% was observed in the simulations and experiments when the sapphire thickness changed from 100um to 200um. But the output power increasing is inconspicuous when the thickness is more than 200um. The structure on bottom face of sapphire substrates can enhance the extraction efficiency of GaN-based LED, too. The difference of output power between the flip-chip LED with smooth bottom surface and the LED with roughness bottom surface is about 50%, where only a common sapphire grinding process is used. But for those LEDs grown on patterned sapphire substrate the difference is only about 10%. Another kind of periodic pattern on the bottom of sapphire is fabricated by the dry etch method, and the output of the back-etched LEDs is improved about 50% than a common. case.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A 5GHz low power WLAN transceiver SiGe RFIC for personal communication terminal applications

A low-cost low-power single chip WLAN 802.11a transceiver is designed for personal communication terminal and local multimedia data transmission. It has less than 130mA current dissipation, maximal 67dB gain and can be programmed to be 20dB minimal gain. The receiver system noise figure is 6.4dB in hige-gain mode.

A wide-band front-end for terrestrial and cable receptions

In this paper, a wide-band low noise amplifier, two mixers and a VCO with its buffers implemented in 50GHz 0.35 mu m SiGe BiCMOS technology for dual-conversion digital TV tuner front-end is presented. The LNA and up-converting mixer utilizes current injection technology to achieve high linearity. Without using inductors, the LNA achieves 0.1-1GHz wide bandwidth and 18.8-dB gain with less than 1.4-dB gain variation. The noise figure of the LNA is less than 5dB and its 1dB compression point is -2 dBm. The IIP3 of two mixers is 25-dBm. The measurement results show that the VCO has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole chip consume 253mW power with 5-V supply.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.