Investigation of numerical atomic orbitals for first-principles calculations of the electronic and transport properties of silicon nanowire structures

This thesis is focused on the application of numerical atomic basis sets in studies of the structural, electronic and transport properties of silicon nanowire structures from first-principles within the framework of Density Functional Theory. First we critically examine the applied methodology and then offer predictions regarding the transport properties and realisation of silicon nanowire devices. The performance of numerical atomic orbitals is benchmarked against calculations performed with plane waves basis sets. After establishing the convergence of total energy and electronic structure calculations with increasing basis size we have shown that their quality greatly improves with the optimisation of the contraction for a fixed basis size. The double zeta polarised basis offers a reasonable approximation to study structural and electronic properties and transferability exists between various nanowire structures. This is most important to reduce the computational cost. The impact of basis sets on transport properties in silicon nanowires with oxygen and dopant impurities have also been studied. It is found that whilst transmission features quantitatively converge with increasing contraction there is a weaker dependence on basis set for the mean free path; the double zeta polarised basis offers a good compromise whereas the single zeta basis set yields qualitatively reasonable results. Studying the transport properties of nanowire-based transistor setups with p+-n-p+ and p+-i-p+ doping profiles it is shown that charge self-consistency affects the I-V characteristics more significantly than the basis set choice. It is predicted that such ultrascaled (3 nm length) transistors would show degraded performance due to relatively high source-drain tunnelling currents. Finally, it is shown the hole mobility of Si nanowires nominally doped with boron decreases monotonically with decreasing width at fixed doping density and increasing dopant concentration. Significant mobility variations are identified which can explain experimental observations.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Non Classical Design in MOSFETs for Improving OTA gain-bandwidth trade off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .

Characterization of Nickel Germanide Schottky Contacts for the Fabrication of Germanium p-channel MOSFETs

Nickel germanide Schottky contacts, formed by rapid thermal annealing of thin nickel films, have been characterized on n-type germanium wafers for a range of RTA temperatures. The highest Schottky barrier heights for electrons (= 0.6-0.7 eV) were obtained for RTA temperatures of approximately 300°C. For this RTA schedule, the corresponding barrier height for holes is close to zero, ideal for Schottky contacted p-channel germanium MOSFETs. When the RTA temperature was increased to 400oC, a dramatic reduction in electron barrier height (< 0.1 eV) was observed. This RTA schedule, therefore, appears ideal for ohmic source/drain contacts to n channel germanium MOSFETs. From sheet resistance measurements and XRD characterization, nickel germanide formation was found to occur at 300oC and above. The NiGe phase was dominant for RTA temperatures up to at least 435oC.

Exposure modelling to traffic-related air toxic pollutants

Atualmente, a poluição atmosférica constitui uma das principais causas ambientais de mortalidade. Cerca de 30% da população europeia residente em áreas urbanas encontra-se exposta a níveis de poluição atmosférica superiores aos valores- limite de qualidade do ar legislados para proteção da saúde humana, representando o tráfego rodoviário uma das principais fontes de poluição urbana. Além dos poluentes tradicionais avaliados em áreas urbanas, os poluentes classificados como perigosos para a saúde (Hazard Air Pollutants - HAPs) têm particular relevância devido aos seus conhecidos efeitos tóxicos e cancerígenos. Neste sentido, a avaliação da exposição tornase primordial para a determinação da relação entre a poluição atmosférica urbana e efeitos na saúde. O presente estudo tem como principal objetivo o desenvolvimento e implementação de uma metodologia para avaliação da exposição individual à poluição atmosférica urbana relacionada com o tráfego rodoviário. De modo a atingir este objetivo, foram identificados os parâmetros relevantes para a quantificação de exposição e analisados os atuais e futuros potenciais impactos na saúde associados com a exposição à poluição urbana. Neste âmbito, o modelo ExPOSITION (EXPOSure model to traffIc-relaTed aIr pOllutioN) foi desenvolvido baseado numa abordagem inovadora que envolve a análise da trajetória dos indivíduos recolhidas por telemóveis com tecnologia GPS e processadas através da abordagem de data mining e análise geoespacial. O modelo ExPOSITION considera também uma abordagem probabilística para caracterizar a variabilidade dos parâmetros microambientais e a sua contribuição para exposição individual. Adicionalmente, de forma a atingir os objetivos do estudo foi desenvolvido um novo módulo de cálculo de emissões de HAPs provenientes do transporte rodoviário. Neste estudo, um sistema de modelação, incluindo os modelos de transporteemissões- dispersão-exposição, foi aplicado na área urbana de Leiria para quantificação de exposição individual a PM2.5 e benzeno. Os resultados de modelação foram validados com base em medições obtidas por monitorização pessoal e monitorização biológica verificando-se uma boa concordância entre os resultados do modelo e dados de medições. A metodologia desenvolvida e implementada no âmbito deste trabalho permite analisar e estimar a magnitude, frequência e inter e intra-variabilidade dos níveis de exposição individual, bem como a contribuição de diferentes microambientes, considerando claramente a sequência de eventos de exposição e relação fonte-recetor, que é fundamental para avaliação dos efeitos na saúde e estudos epidemiológicos. O presente trabalho contribui para uma melhor compreensão da exposição individual em áreas urbanas, proporcionando novas perspetivas sobre a exposição individual, essenciais na seleção de estratégias de redução da exposição à poluição atmosférica urbana, e consequentes efeitos na saúde.

Sedimentology and Geochemistry of core sediments from the Ashtamudi estuary and the adjoining coastal plain,central Kerala,India

The evolution of coast through geological time scale is dependent on the transgression-regression event subsequent to the rise or fall of sea level. This event is accounted by investigation of the vertical sediment deposition patterns and their interrelationship for paleo-enviornmental reconstruction. Different methods like sedimentological (grain size and micro-morphological) and geochemical (elemental relationship) analyses as well as radiocarbon dating are generally used to decipher the sea level changes and paleoclimatic conditions of the Quaternary sediment sequence. For the Indian coast with a coastline length of about 7500 km, studies on geological and geomorphological signatures of sea level changes during the Quaternary were reported in general by researchers during the last two decades. However, for the southwest coast of India particularily Kerala which is famous for its coastal landforms comprising of estuaries, lagoons, backwaters, coastal plains, cliffs and barrier beaches, studies pertaining to the marine transgression-regression events in the southern region are limited. The Neendakara-Kayamkulam coastal stretch in central Kerala where the coast is manifested with shore parallel Kayamkulam Lagoon on one side and shore perpendicular Ashtamudi Estuary on the other side indicating existence of an uplifted prograded coastal margin followed by barrier beaches, backwater channels, ridge and runnel topography is an ideal site for studying such events. Hence the present study has been taken up in this context to address the gap area. The location for collection of core samples representing coastal plain, estuarylagoon and offshore regions have been identified based on published literature and available sedimentary records. The objectives of the research work are:  To study the lithological variations and depositional environments of sediment cores along the coastal plain, estuary-lagoon and offshore regions between Kollam and Kayamkulam in the central Kerala coast  To study the transportation and diagenetic history of sediments in the area  To investigate the geochemical characterization of sediments and to elucidate the source-sink relationship  To understand the marine transgression-regression events and to propose a conceptual model for the region The thesis comprises of 8 chapters. The first chapter embodies the preamble for the selection and significance of this research work. The study area is introduced with details on its physiographical, geological, geomorphological, rainfall and climate information. A review of literature, compiling the research on different aspects such as physico-chemical, geomorphological, tectonics, transgression-regression events are presented in the second chapter and they are broadly classified into three viz:- International, National and Kerala. The field data collection and laboratory analyses adopted in the research work are discussed in the third chapter. For collection of sediment core samples from the coastal plains, rotary drilling method was employed whereas for the estuary-lagoon and offshore locations the gravity/piston corer method was adopted. The collected subsurficial samples were analysed for texture, surface micro-texture, elemental analysis, XRD and radiocarbon dating techniques for age determination. The fourth chapter deals with the textural analysis of the core samples collected from various predefined locations of the study area. The result reveals that the Ashtamudi Estuary is composed of silty clay to clayey type of sediments whereas offshore cores are carpeted with silty clay to relict sand. Investigation of the source of sediments deposited in the coastal plain located on either side of the estuary indicates the dominance of terrigenous to marine origin in the southern region whereas it is predominantly of marine origin towards the north. Further the hydrodynamic conditions as well as the depositional enviornment of the sediment cores are elucidated based on statistical parameters that decipher the deposition pattern at various locations viz., coastal plain (open to closed basin), Ashtamudi Estuary (partially open to restricted estuary to closed basin) and offshore (open channel). The intensity of clay minerals is also discussed. From the results of radiocarbon dating the sediment depositional environments were deciphered.The results of the microtextural study of sediment samples (quartz grains) using Scanning Electron Microscope (SEM) are presented in the fifth chapter. These results throw light on the processes of transport and diagenetic history of the detrital sediments. Based on the lithological variations, selected quartz grains of different environments were also analysed. The study indicates that the southern coastal plain sediments were transported and deposited mechanically under fluvial environment followed by diagenesis under prolonged marine incursion. But in the case of the northern coastal plain, the sediments were transported and deposited under littoral environment indicating the dominance of marine incursion through mechanical as well as chemical processes. The quartz grains of the Ashtamudi Estuary indicate fluvial origin. The surface texture features of the offshore sediments suggest that the quartz grains are of littoral origin and represent the relict beach deposits. The geochemical characterisation of sediment cores based on geochemical classification, sediment maturity, palaeo-weathering and provenance in different environments are discussed in the sixth chapter. In the seventh chapter the integration of multiproxies data along with radiocarbon dates are presented and finally evolution and depositional history based on transgression–regression events is deciphered. The eighth chapter summarizes the major findings and conclusions of the study with recommendation for future work.

Effects of shoot pruning and inflorescence thinning on plant growth, yield and fruit quality of greenhouse tomatoes in a tropical climate

The combined effects of shoot pruning (one or two stems) and inflorescence thinning (five or ten flowers per inflorescence) on greenhouse tomato yield and fruit quality were studied during the dry season (DS) and rainy season (RS) in Central Thailand. Poor fruit set, development of undersized (mostly parthenocarpic) fruits, as well as the physiological disorders blossom-end rot (BER) and fruit cracking (FC) turned out to be the prevailing causes deteriorating fruit yield and quality. The proportion of marketable fruits was less than 10% in the RS and around 65% in the DS. In both seasons, total yield was significantly increased when plants were cultivated with two stems, resulting in higher marketable yields only in the DS. While the fraction of undersized fruits was increased in both seasons when plants were grown with a secondary stem, the proportions of BER and FC were significantly reduced. Restricting the number of flowers per inflorescence invariably resulted in reduced total yield. However, in neither season did fruit load considerably affect quantity or proportion of the marketable yield fraction. Inflorescence thinning tended to promote BER and FC, an effect which was only significant for BER in the RS. In conclusion, for greenhouse tomato production under climate conditions as they are prevalent in Central Thailand, the cultivation with two stems appears to be highly recommendable whereas the measures to control fruit load tested in this study did not proof to be advisable.

Seed Cell Wall Storage Polysaccharides: Models to Understand Cell Wall Biosynthesis and Degradation

Cell wall storage polysaccharides (CWSPs) are found as the principal storage compounds in seeds of many taxonomically important groups of plants. These groups developed extremely efficient biochemical mechanisms to disassemble cell walls and use the products of hydrolysis for growth. To accumulate these storage polymers, developing seeds also contain relatively high activities of noncellulosic polysaccharide synthases and thus are interesting models to seek the discovery of genes and enzymes related to polysaccharide biosynthesis. CWSP systems offer opportunities to understand phenomena ranging from polysaccharide deposition during seed maturation to the control of source-sink relationship in developing seedlings. By studying polysaccharide biosynthesis and degradation and the consequences for cell and physiological behavior, we can use these models to develop future biotechnological applications.