A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

Direct Wafer Bonding Technology employing vacuum-cavity pre-bonding

A novel low temperature direct wafer bonding technology employing vacuum-cavity pre-bonding is proposed and applied in bonding of InGaAs/Si couple wafers under 300 degrees C and InP/GaAs couple wafers under 350 degrees C. Aligning accuracy of 0.5 mu m is achieved. During wafer bonding process the pressure on the couple wafers is 10MPa. The interface energy is sufficiently high to allow thinning of the wafers down from 350um to about 100um. And the tensile strength test indicates the bonding energy of bonded samples is about equal to the bonded samples at 550 degrees C.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Scale study of direct synthesis of dimethyl ether from biomass synthesis gas

We investigated the synthesis of dimethyl ether (DME) from biomass synthesis gas using a kind of hybrid catalyst consisting of methanol and HZSM-5 zeolite in a fixed-bed reactor in a 100 ton/year pilot plant. The biomass synthesis gas was produced by oxygen-rich gasification of corn core in a two-stage fixed bed. The results showed that CO conversions reached 82.00% and 73.55%, the selectivities for DME were 73.95% and 69.73%, and the space-time yields were 124.28 kg m- 3 h- 1 and 203.80 kg m- 3 h- 1 when gas hourly space velocities were 650 h- 1 and 1200 h- 1, respectively. Deoxidation and tar removal from biomass synthesis gas was critical to the stable operation of the DME synthesis system. Using single-pass synthesis, the H2/CO ratio improved from 0.98-1.17 to 2.12-2.22. The yield of DME would be increased greatly if the exhaust was reused after removal of the CO2.

低甲醇透过直接甲醇燃料电池(Low Methanol Crossover Direct Methanol Fuel Cell)

直接甲醇燃料电池与间接甲醇燃料电池相比，体积更小，重量更轻，因此在一些领域有诱人的应用前景。但是，在它们实际应用之前，必须解决一些具体的技术难题。目前，甲醇从阳极透过到阴极是影响电池性能的主要难题之一，另外，催化剂和电极的制备方法也对电池的性能有重要的影响。本论文的主要目的在于研制低甲醇透过直接甲醇燃料电池并有效地提高电池的性能。为了减小甲醇在Nafion117膜中的透过，提出并研制了铭纳米粒子修饰的Nafion复合膜，该方法包括与[Pd(NH_4)_4]~(2+)离子的离子交换过程和化学还原过程。研究了一种制备高分散性铂基催化剂的方法。另外我们还研究并分析了不同的电池运行参数，例如温度、甲醇浓度等，刘一电池性能和甲醇透过的影响。主要结果如下：1.采用离子交换还原法在Nafionll7膜内部沉积纳米把粒子，制备成高聚物电解质复合膜。研究了镀把前后Nafion膜表面形态、甲醇透过和膜的电导的变化和对直接甲醇燃料电池的性能的影响等。由于把纳米粒子阻碍了甲醇透过，同时，由于它对氢离子的强吸引力，不但不对氢离子的透过产生影响，而且还提高了膜佩狗电导。所以镀把后电解质膜的甲醇透过减少，膜电导增加，无论在低电流密度区还是在高电流密度区，电池性能都有效地提高。2.研究了一种制备高分散性铂基催化剂的新方法一预沉淀还原法。并采用TEM,XRD和电化学等技术来表征催化剂中铂的粒径、晶态结构和催化活性：与传统的化学还原法相比，因为该方法在化学还原过程中反应物与载体的作用力得到增强，所以采用该方法制备的催化剂铂分散性更好、晶态结构更低、粒径更小并且催化活性更好。该方法在直接甲醇燃料一电池中有应用价值。3.研究并分析了不同的电池运行参数，例如温度、甲醇浓度等，对电池性能和甲醇透过的影响。研究发现当电池运行温度增加时，电池性能提高，甲醇透过增加；甲醇浓度增加时，甲醇透过增加，但是，甲醇浓度对电池性能有不同的影响，在低甲醇浓度区，甲醇浓度增加，电池性能提高；在高甲醇浓度区，甲醇浓度增加，电池性能降低；存在一个最佳甲醇浓度，在该甲醇浓度的条件下，电池的性能最高。实验结果为：采用Nafion117膜时，电池的最佳甲醇浓度为2. 0 mol/L，采用镀把Nafion117膜时，电池的最佳甲醇浓度高于4.0 mol/Lo