1000 resultados para Fuel fabrication


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直接甲醇燃料电池与间接甲醇燃料电池相比,体积更小,重量更轻,因此在一些领域有诱人的应用前景。但是,在它们实际应用之前,必须解决一些具体的技术难题。目前,甲醇从阳极透过到阴极是影响电池性能的主要难题之一,另外,催化剂和电极的制备方法也对电池的性能有重要的影响。本论文的主要目的在于研制低甲醇透过直接甲醇燃料电池并有效地提高电池的性能。为了减小甲醇在Nafion117膜中的透过,提出并研制了铭纳米粒子修饰的Nafion复合膜,该方法包括与[Pd(NH_4)_4]~(2+)离子的离子交换过程和化学还原过程。研究了一种制备高分散性铂基催化剂的方法。另外我们还研究并分析了不同的电池运行参数,例如温度、甲醇浓度等,刘一电池性能和甲醇透过的影响。主要结果如下:1.采用离子交换还原法在Nafionll7膜内部沉积纳米把粒子,制备成高聚物电解质复合膜。研究了镀把前后Nafion膜表面形态、甲醇透过和膜的电导的变化和对直接甲醇燃料电池的性能的影响等。由于把纳米粒子阻碍了甲醇透过,同时,由于它对氢离子的强吸引力,不但不对氢离子的透过产生影响,而且还提高了膜佩狗电导。所以镀把后电解质膜的甲醇透过减少,膜电导增加,无论在低电流密度区还是在高电流密度区,电池性能都有效地提高。2.研究了一种制备高分散性铂基催化剂的新方法一预沉淀还原法。并采用TEM,XRD和电化学等技术来表征催化剂中铂的粒径、晶态结构和催化活性:与传统的化学还原法相比,因为该方法在化学还原过程中反应物与载体的作用力得到增强,所以采用该方法制备的催化剂铂分散性更好、晶态结构更低、粒径更小并且催化活性更好。该方法在直接甲醇燃料一电池中有应用价值。3.研究并分析了不同的电池运行参数,例如温度、甲醇浓度等,对电池性能和甲醇透过的影响。研究发现当电池运行温度增加时,电池性能提高,甲醇透过增加;甲醇浓度增加时,甲醇透过增加,但是,甲醇浓度对电池性能有不同的影响,在低甲醇浓度区,甲醇浓度增加,电池性能提高;在高甲醇浓度区,甲醇浓度增加,电池性能降低;存在一个最佳甲醇浓度,在该甲醇浓度的条件下,电池的性能最高。实验结果为:采用Nafion117膜时,电池的最佳甲醇浓度为2. 0 mol/L,采用镀把Nafion117膜时,电池的最佳甲醇浓度高于4.0 mol/Lo

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InGaN/GaN multiple quantum well-based light-emitting diode (LED) nanopillar arrays were fabricated using Ni self-assembled nanodots as etching mask. The Ni nanodots were fabricated with a density of 6 x 10(8)-1.5 x 10(9) cm(-2) and a dimension of 100-250 nm with varying Ni thickness and annealing duration time. Then LED nanopillar arrays with diameter of approximately 250 nm and height of 700 nm were fabricated by inductively coupled plasma etching. In comparison to the as-grown LED sample an enhancement by a factor of four of photoluminescence (PL) intensity is achieved for the nanopillars and a blueshift as well as a decrease in full width at half maximum of the PL peak are also observed. The method of additional chemical etching was used to remove the etching-induced damage. Then nano-LED devices were further completed using a planarization approach to deposit p-type electrode on the tips of nanopillars. The current-voltage curves of both nanopillars and planar LED devices are measured for comparison.

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A convenient fabrication technology for large-area, highly-ordered nanoelectrode arrays on silicon substrate has been described here, using porous anodic alumina (PAA) as a template. The ultrathin PAA membranes were anodic oxidized utilizing a two-step anodization method, from Al film evaporated on substrate. The purposes for the use of two-step anodization were, first, improving the regularity of the porous structures, and second reducing the thickness of the membranes to 100 similar to 200 nm we desired. Then the nanoelectrode arrays were obtained by electroless depositing Ni-W alloy into the through pores of PAA membranes, making the alloy isolated by the insulating pore walls and contacting with the silicon substrates at the bottoms of pores. The Ni-W alloy was also electroless deposited at the back surface of silicon to form back electrode. Then ohmic contact properties between silicon and Ni-W alloy were investigated after rapid thermal annealing. Scanning electron microscopy (SEM) observations showed the structure characteristics, and the influence factors of fabrication effect were discussed. The current voltage (I-V) curves revealed the contact properties. After annealing in N-2 at 700 degrees C, good linear property was shown with contact resistance of 33 Omega, which confirmed ohmic contacts between silicon and electrodes. These results presented significant application potential of this technology in nanosize current-injection devices in optoelectronics, microelectronics and bio-medical fields.

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A comparatively low-quality silicon wafer (with a purity of almost-equal-to 99.9%) was adopted to form a silicon-on-defect-layer (SODL) structure featuring improved crystalline silicon near the defect layer (DL) by means of proton implantation and subsequent annealing. Thus, the SODL technique provides an opportunity to enable low-quality silicon wafers to be used for fabrication of low-cost solar cells.

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High efficiency AlxGa1-xAs/GaAs heteroface solar cells have been fabricated by an improved multi-wafer squeezing graphite boat liquid phase epitaxy (LPE) technique, which enables simultaneous growth of twenty 2.3 X 2.3cm(2) epilayers in one run. A total area conversion efficiency of 17.33% is exhibited (1sun, AM0, 2.0 x 2.0cm(2)). The shallow junction cell shows more resistance to 1 MeV electron radiation than the deep one. After isochronal or isothermal annealing the density and the number of deep level traps induced by irradiation are reduced effectively for the solar cells with deep junction and bombardment under high electron fluences.

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A lithography-independent and wafer scale method to fabricate a metal nanogap structure is demon-strated. Polysilicon was first dry etched using photoresist (PR) as the etch mask patterned by photolithography.Then, by depositing conformal SiO_2 on the polysilicon pattern, etching back SiO_2 anisotropically in the perpendic-ular direction and removing the polysilicon with KOH, a sacrificial SiO_2 spacer was obtained. Finally, after metal evaporation and lifting-off of the SiO_2 spacer, an 82 nm metal-gap structure was achieved. The size of the nanogap is not determined by the photolithography, but by the thickness of the SiO_2. The method reported in this paper is compatible with modern semiconductor technology and can be used in mass production.

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Silicon crystal-facet-dependent nanostructures have been successfully fabricated on a (100)-oriented silicon-on-insulator wafer using electron-beam lithography and the silicon anisotropic wet etching technique. This technique takes ad-vantage of the large difference in etching properties for different crystallographic planes in alkaline solution. The mini-mum size of the trapezoidal top for those Si nanostructures can be reduced to less than 10nm. Scanning electron microscopy(SEM) and atomic force microscopy (AFM) observations indicate that the etched nanostructures have controllable shapes and smooth surfaces.

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A high performance AlAs/In0.53 Ga0.47 As/InAs resonant tunneling diode (RTD) on InP substrate is fabricated by inductively coupled plasma etching. This RTD has a peak-to-valley current ratio (PVCR) of 7. 57 and a peak current density Jp = 39.08kA/cm^2 under forward bias at room temperature. Under reverse bias, the corresponding values are 7.93 and 34.56kA/cm^2 . A resistive cutoff frequency of 18.75GHz is obtained with the effect of a parasitic probe pad and wire. The slightly asymmetrical current-voltage characteristics with a nominally symmetrical structure are also discussed.