Coordinated control of DFIG’s rotor and grid side converters during network unbalance

This paper proposes a coordinated control of the rotor and grid side converters (RSC & GSC) of doubly-fed induction generator (DFIG) based wind generation systems under unbalanced voltage conditions. System behaviors and operations of the RSC and GSC under unbalanced voltage are illustrated. To provide enhanced operation, the RSC is controlled to eliminate the torque oscillations at double supply frequency under unbalanced stator supply. The oscillation of the stator output active power is then cancelled by the active power output from the GSC, to ensure constant active power output from the overall DFIG generation system. To provide the required positive and negative sequence currents control for the RSC and GSC, a current control strategy containing a main controller and an auxiliary controller is analyzed. The main controller is implemented in the positive (dq)+ frame without involving positive/negative sequence decomposition whereas the auxiliary controller is implemented in the negative sequence (dq)? frame with negative sequence current extracted. Simulation results using EMTDC/PSCAD are presented for a 2MW DFIG wind generation system to validate the proposed control scheme and to show the enhanced system operation during unbalanced voltage supply.

The Langmuir probe as a diagnostic of the electron component within low temperature laser ablated plasma plumes

A Langmuir probe has been used as a diagnostic of the temporally evolving electron component within a laser ablated Cu plasma expanding into vacuum, for an incident laser power density on target similar to that used for the pulsed laser deposition of thin films. Electron temperature data were obtained from the retarding region of the probe current/voltage (I/V) characteristic, which was also used to calculate an associated electron number density. Additionally, electron number density data were obtained from the saturation electron current region of the probe (I/V) characteristic. Electron number density data, extracted by the two different techniques, were observed to show the same temporal form, with measured absolute values agreeing to within a factor of 2. The Langmuir probe, in the saturation current region, has been shown for the first time to be a convenient diagnostic of the electron component within relatively low temperature laser ablated plasma plumes. (C) 1999 American Institute of Physics. [S0034-6748(99)01503-8].

TEMPORALLY AND SPATIALLY-RESOLVED PLASMA PARAMETERS AND EEDF MEASUREMENTS IN A LOW-FREQUENCY DISCHARGE

A time-resolved Langmuir probe technique is used to measure the dependence of the electron density, electron temperature, plasma potential and electron energy distribution function (EEDF) on the phase of the driving voltage in a RF driven parallel plate discharge. The measurements were made in a low-frequency (100-500 kHz), symmetrically driven, radio frequency discharge operating in H-2, D-2 and Ar at gas pressures of a few hundred millitorr. The EEDFs could not be represented by a single Maxwellian distribution and resembled the time averaged EEDFs reported in 13.56 MHz discharges. The measured parameters showed structure in their spatial and temporal dependence, generally consistent with a simple oscillating sheath model. Electron temperatures of less than 0.1 eV were measured during the phase of the RF cycle when both electrodes are negative with respect to the plasma.

The Bright Side of Manufacturing–Remanufacturing Conflict in a Decentralised Closed-Loop Supply Chain

Researchers and managers broadly agree that original equipment manufacturers (OEMs), which have opportunities to produce both new and remanufactured products, are better off by centrally controlling their manufacturing and remanufacturing activities. Thus, OEMs should not remanufacture used products until the remanufacturing cost is sufficiently low to overcome the negative impact of new product cannibalisation. In this paper, we present a contrasting view of the manufacturing–remanufacturing conflict: OEMs sometimes benefit from the decentralised control mode under which they ignore the internal cannibalisation rather than the remanufacturing option. We consider a decentralised closed-loop supply chain in which one OEM can purchase new components from one supplier to produce new products and collect used products from consumers to produce remanufactured products. The key feature of our model is that the OEM can select a centralised or decentralised control mode to manage its manufacturing and remanufacturing activities before the supplier prices the new component. In a steady state period setting, we analyse the players’ optimal decisions and compare the OEM's profits under centralised and decentralised control modes. Our analytic results reveal that the decentralised control within the OEM can outperform the centralised control when the cost structure of producing new and remanufactured products satisfies certain conditions. Finally, the key findings are distilled in a conceptual framework and its managerial implications are discussed.

Capability Curve Based Enhanced Reactive Power Control Strategy for Stability Enhancement and Network Voltage Management

Reactive power has become a vital resource in modern electricity networks due to increased penetration of distributed generation. This paper examines the extended reactive power capability of DFIGs to improve network stability and capability to manage network voltage profile during transient faults and dynamic operating conditions. A coordinated reactive power controller is designed by considering the reactive power capabilities of the rotor-side converter (RSC) and the grid-side converter (GSC) of the DFIG in order to maximise the reactive power support from DFIGs. The study has illustrated that, a significant reactive power contribution can be obtained from partially loaded DFIG wind farms for stability enhancement by using the proposed capability curve based reactive power controller; hence DFIG wind farms can function as vital dynamic reactive power resources for power utilities without commissioning additional dynamic reactive power devices. Several network adaptive droop control schemes are also proposed for network voltage management and their performance has been investigated during variable wind conditions. Furthermore, the influence of reactive power capability on network adaptive droop control strategies has been investigated and it has also been shown that enhanced reactive power capability of DFIGs can substantially improve the voltage control performance.

Polymer electrolyte membrane water electrolyser with Aquivion short side chain perfluorosulfonic acid ionomer binder in catalyst layers

The Aquivion short-side-chain (SSC) perfluorosulfonic acid (PFSA) ionomer was adopted in catalyst layers (CL) of polymer electrolyte membrane water electrolysers (PEMWE) instead of long-side-chain (LSC) Nafion ionomer. The effects of SSC ionomer content in CL for oxygen evolution reaction were studied in half cell with cyclic voltammetry and steady state linear sweep. In a single cell test the MEA with SSC-PFSA Aquivion ionomer exhibited better thermal stability than the one with LSC-PFSA Nafion ionomer at 90 °C. The cell voltage at a current density of 1 A cm was 1.63 V at 90 °C using the SSC-PFSA Aquivion ionomer binder, Nafion 117 membrane, and without back pressurizing. In a continuous operation the cell voltage degradation rate of the MEA using Aquivion ionomer binder was only about 0.82 mV h.

Holistic design of 8-way combining transformers in SiGe technology for use in millimetre-wave power amplifiers

This paper presents the design of a novel 8-way power-combining transformer for use in mm-wave power amplifier (PA). The combiner exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. A complete circuit comprised of a power splitter, two-stage cascode PA array, a power combiner and input/output matching elements was designed and realized in SiGe technology. Measured gain of at least 16.8 dB was obtained from 76.4 GHz to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm OP and 14 dBm saturated output power when operated from a 3.2 V DC supply voltage at 78 GHz. © 2013 IEEE.

A Smart Grid Information System for Demand Side Participation: Remote Control of Domestic Appliances to Balance Demand

Due to the intermittent nature of renewable generation it is desirable to consider the potential of controlling the demand-side load to smooth overall system demand. The architecture and control methodologies of such a system on a large scale would require careful consideration. Some of these considerations are discussed in this paper; such as communications infrastructure, systems architecture, control methodologies and security. A domestic fridge is used in this paper as an example of a controllable appliance. A layered approach to smart-grid is introduced and it can be observed how each smart-grid component from physical cables, to the end-devices (or smart-applications) can be mapped to these set layers. It is clear how security plays an integral part in each component of the smart-grid so this is also an integral part of each layer. The controllable fridge is described in detail and as one potential smart-grid application which maps to the layered approach. A demonstration system is presented which involves a Raspberry Pi (a low-power, low-cost device representing the appliance controller).

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Significance Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator

In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scalable, process variation aware motion estimator based on significance driven computation. The fundamental premise of our approach lies in the fact that all computations are not equally significant in shaping the output response of video systems. We use a statistical technique to intelligently identify these significant/not-so-significant computations at the algorithmic level and subsequently change the underlying architecture such that the significant computations are computed in an error free manner under voltage over-scaling. Furthermore, our design includes an adaptive quality compensation (AQC) block which "tunes" the algorithm and architecture depending on the magnitude of voltage over-scaling and severity of process variations. Simulation results show average power savings of similar to 33% for the proposed architecture when compared to conventional implementation in the 90 nm CMOS technology. The maximum output quality loss in terms of Peak Signal to Noise Ratio (PSNR) was similar to 1 dB without incurring any throughput penalty.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.