Using remote labs to serve different teacher's needs a case study with VISIR and RemotElectLab

Remote Laboratories are an emergent technological and pedagogical tool at all education levels, and their widespread use is an important part of their own improvement and evolution. This paper describes several issues encountered on laboratorial classes, on higher education courses, when using remote laboratories based on PXI systems, either using the VISIR system or an alternate in-house solution. Three main issues are presented and explained, all reported by teachers that gave support to students use of remote laboratories. The first issue deals with the need to allow students to select the actual place where an ammeter is to be inserted on electric circuits, even incorrectly, therefore emulating real world difficulties. The second one deals with problems with timing when several measurements are required at short intervals, as in the discharge cycle of a capacitor. And the last issue deals with the use of a multimeter in DC mode when reading AC values, a use that collides with the lab settings. All scenarios are presented and discussed including the solution found for each case. The conclusion derived from the described work is that the remote laboratories area is an expanding field, where practical use leads to improvement and evolution of the available solutions, requiring a strict cooperation and information sharing between all actors, i.e. developers, teachers and students.

Marx-Type solid-state bipolar modulator topologies: Performance comparison

The operation of generalized Marx-type solid-state bipolar modulators is discussed and compared with simplified Marx-derived circuits, to evaluate their capability to deal with various load conditions. A comparative analysis on the number of switches per cell, fiber optic trigger count, losses, and switch hold-off voltages has been made. A circuit topology is obtained as a compromise in terms of operating performance, trigger simplicity, and switching losses. A five-stage laboratory prototype of this circuit has been assembled using 1200 V insulated gate bipolar transistors (IGBTs) and diodes, operating with 1000 V dc input voltage and 1 kHz frequency, giving 5 kV bipolar pulses, with 2.5 mu s pulse width and 5 mu s relaxation time into resistive, capacitive, and inductive loads.

Transformador diferencial de variação linear: condicionamento de sinal e desmodulação síncrona

Dissertação para obtenção do grau de Mestre em Engenharia Eletrotécnica Ramo de Automação e eletrónica Industrial

Fully transparent ZnO thin-film transistor produced at room temperature

Advanced Materials, Vol. 17, nº 5

Development of fractional order capacitors based on electrolyte processes

In recent years, significant research in the field of electrochemistry was developed. The performance of electrical devices, depending on the processes of the electrolytes, was described and the physical origin of each parameter was established. However, the influence of the irregularity of the electrodes was not a subject of study and only recently this problem became relevant in the viewpoint of fractional calculus. This paper describes an electrolytic process in the perspective of fractional order capacitors. In this line of thought, are developed several experiments for measuring the electrical impedance of the devices. The results are analyzed through the frequency response, revealing capacitances of fractional order that can constitute an alternative to the classical integer order elements. Fractional order electric circuits are used to model and study the performance of the electrolyte processes.

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Projeto de um conversor eletrónico para utilização num sistema eólico de produção de energia

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica no Ramo de Automação e Electrónica Industrial

Projeto e implementação de um pré-regulador de fator de potência com controlo digital

Hoje em dia as fontes de alimentação possuem correção do fator de potência, devido às diversas normas regulamentares existentes, que introduziram grandes restrições no que respeita à distorção harmónica (THD) e fator de potência (FP). Este trabalho trata da análise, desenvolvimento e implementação de um Pré-Regulador de fator de potência com controlo digital. O controlo digital de conversores com recurso a processamento digital de sinal tem vindo a ser ao longo dos últimos anos, objeto de investigação e desenvolvimento, estando constantemente a surgirem modificações nas topologias existentes. Esta dissertação tem como objetivo estudar e implementar um Pré-Regulador Retificador Boost e o respetivo controlo digital. O controlo do conversor é feito através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado num dispositivo FPGA (Field Programmable Gate Array) Spartan-3E. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos controladores. Para efetuar este controlo é necessário adquirir os sinais da corrente de entrada, tensão de entrada e tensão de saída. O sinal resultante do módulo de controlo é um sinal de PWM com valor de fator de ciclo variável ao longo do tempo. O projeto é simulado e validado através da plataforma MatLab/Simulink e PSIM, onde são apresentados resultados para o regime permanente e para transitórios da carga e da tensão de alimentação. Finalmente, o Pré-Regulador Retificador Boost controlado de forma digital é implementado em laboratório. Os resultados experimentais são apresentados para validar a metodologia e o projeto desenvolvidos.

Implementação de um Array de detetores de radiação ionizante

Atualmente, as radiações ionizantes desempenham um papel fundamental nas áreas de diagnóstico e terapia, estando omnipresentes em ambientes hospitalares. Contudo, devido aos efeitos biológicos adversos da radiação, torna-se essencial a protecção dos profissionais de saúde e pacientes. Consequentemente, um array de detetores capazes de produzir um sinal acústico, aquando da presença de radiação ionizante excedendo determinados valores limite e transmissão via wireless das leituras para um sistema central _e de grande interesse prático. Nesta dissertação, foi implementado um sistema capaz de alimentar um array de sensores de radiação para monitorização de diferentes espaços e transmissão das leituras efetuadas via wireless. A aquisição de dados foi realizada, recorrendo à utilização de um conversor analógico-digital. Vários testes de validação foram realizados, através de vários passos para alcançar a concretização do sistema final, nomeadamente testes relativos ao circuito de detecção, módulos de comunicação wireless, bem como o uso de diferentes ambientes de desenvolvimento integrados (IDE). Os resultados destes testes mostram a visualização e gravação adequadas dos dados relativos aos níveis de radiação, bem como a transmissão de dados de forma viável, permitindo a monitorização de espaços sujeitos à presença de radiação ionizante. Desta forma, um array de contadores Geiger-Müller, ligados a módulos wireless XBee open-source e uma placa Arduino, possibilitou a implementação de um sistema viável e de baixo custo para monitorização de radiação ionizante e registar esses mesmos dados para posterior análise.

New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise

IEEE International Symposium on Circuits and Systems, pp. 232 – 235, Seattle, EUA

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA

A CMOS variable width short-pulse generator circuit for UWB RADAR applications

IEEE International Symposium on Circuits and Systems, pp. 2713 – 2716, Seattle, EUA