A framework for fault tolerant real time systems based on reconfigurable FPGAs


Autoria(s): Gericota, Manuel G.; Lemos, L. F.; Alves, Gustavo R.; Barbosa, M. M.; Ferreira, José M.
Data(s)

03/07/2014

03/07/2014

2006

Resumo

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

Identificador

DOI 10.1109/ETFA.2006.355409

0-7803-9758-4

http://hdl.handle.net/10400.22/4670

Idioma(s)

eng

Publicador

IEEE

Relação

Emerging Technologies and Factory Automation;

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4178242

Direitos

closedAccess

Tipo

conferenceObject