Investigation on the N-eff reverse annealing effect using TSC/I-DLTS: Relationship between neutron induced microscopic defects and silicon detector electrical degradations

Neutron induced defect levels in high resistivity silicon detectors have been studied using a current-based macroscopic defect analysis system: thermally stimulated current (TSC) and current deep level transient spectroscopy (I-DLTS). These studies have been correlated to the traditional C-V, I-V, and transient current and charge techniques (TCT/TChT) after neutron radiation and subsequent thermal anneals. It has been found that the increases of the space charge density, N-eff, in irradiated detectors after thermal anneals (N-eff reverse anneal) correspond to the increases of deep levels in the silicon bandgap. In particular, increases of the double vacancy center (V-V and V-V-- -) and/or C-i-O-i level have good correlations with the N-eff reverse anneal. It has also been observed that the leakage current of highly irradiated (Phi(n) > 10(13) n/cm(2)) detectors increases after thermal anneals, which is different from the leakage current annealing behavior of slightly irradiated (Phi(n) < 10(13) n/cm(2)) detectors. It is apparent that V-V center and/or C-i-O-i level play important roles in both N-eff and leakage current degradations for highly irradiated high resistivity silicon detectors.

DEVELOPMENT OF CURRENT-BASED MICROSCOPIC DEFECT ANALYSIS-METHODS AND ASSOCIATED OPTICAL FILLING TECHNIQUES FOR THE INVESTIGATION ON HIGHLY IRRADIATED HIGH-RESISTIVITY SILICON DETECTORS

Current based microscopic defect analysis methods such as current deep level transient spectroscopy (I-DLTS) and thermally stimulated current (TSC) have been further developed in accordance with the need for the defect analysis of highly irradiated (Phi(n) > 10(13) n/cm(2)) high resistivity silicon detectors. The new I-DLTS/TSC system has a temperature range of 8 K less than or equal to T less than or equal to 450 K and a high sensitivity that can detect a defect concentration of less than 10(10)/cm(3) (background noise as low as 10 fA). A new filling method using different wavelength laser illumination has been applied, which is more efficient and suitable than the traditional voltage pulse filling. It has been found that the filling of a defect level depends on such factors as the total concentration of free carriers generated or injected, the penetration length of the laser (laser wavelength), the temperature at which the filling is taking place, as well as the decay time after the filling (but before the measurement). The mechanism of the defect filling can be explained by the competition between trapping and detrapping of defect levels, possible capture cross section temperature dependence, and interaction among various defect levels in terms of charge transferring. Optimum defect filling conditions have been suggested for highly irradiated high resistivity silicon detectors.

Dependence of wet etch rate on deposition, annealing conditions and etchants for PECVD silicon nitride film

The influence of deposition, annealing conditions, and etchants on the wet etch rate of plasma enhanced chemical vapor deposition (PECVD) silicon nitride thin film is studied. The deposition source gas flow rate and annealing temperature were varied to decrease the etch rate of SiN_x:H by HF solution. A low etch rate was achieved by increasing the SiH_4 gas flow rate or annealing temperature, or decreasing the NH_3 and N_2 gas flow rate. Concen-trated, buffered, and dilute hydrofluoric acid were utilized as etchants for SiO_2 and SiN_x:H. A high etching selectivity of SiO_2 over SiN_x:H was obtained using highly concentrated buffered HF.

Epitaxial growth on 4H-SiC by TCS as a silicon precursor

Epitaxial growth on n-type 4H-SiC 8°off-oriented substrates with a size of 10 × 10 mm~2 at different tem-peratures with various gas flow rates has been performed in a horizontal hot wall CVD reactor, using trichlorosilane (TCS) as a silicon precursor source together with ethylene as a carbon precursor source. The growth rate reached 23 μm/h and the optimal epilayer was obtained at 1600 ℃ with a TCS flow rate of 12 sccm in C/Si of 0.42, which has a good surface morphology with a low RMS of 0.64 nm in an area of 10 × 10μm~2. The homoepitaxial layer was oh-tained at 1500 ℃ with low growth rate (< 5μm/h) and the 3C-SiC epilayers were obtained at 1650 ℃ with a growth rate of 60-70μm/h. It is estimated that the structural properties of the epilayers have a relationship with the growth temperature and growth rate. Silicon droplets with different sizes are observed on the surface of the homoepitaxial layer in a low C/Si ratio of 0.32.

Influence of zinc phthalocyanines on photoelectrical properties of hydrogenated amorphous silicon

Composites consisting of hydrogenated amorphous silicon (a-Si: H, inorganic) and zinc phthalocyanine (ZnPc, organic) were prepared by vacuum evaporation of ZnPc and sequential deposition amorphous silicon via plasma enhanced chemical vapor deposition (PECVD). The optical and electrical properties of the composite film have been investigated. The results demonstrate that ZnPc can endure the temperature and bombardment of the PECVD plasma and photoconductivity of the composite film was improved by 89.9% compared to pure a-Si: H film. Electron mobility-lifetime products μτ of the composite film were increased by nearly one order of magnitude from 6.96 × 10~(-7) to 5.08 × 10~(-6) cm~2/V. Combined with photoconductivity spectra of the composites and pure a-Si: H, we tentatively elucidate the improvement in photoconductivity of the composite film.

Triplexers Based on SOI Flattop AWGs

Triplexers are designed based on SOl flattop arrayed waveguide gratings （AWGs）. Three wavelengths （1310, 1490,and 1550nm） operate at three diffraction orders of AWGs. Simulation shows that the 3dB bandwidth,crosstalk, and loss are 6nm,less than -40dB, and 5dB, respectively. The output optical fields of the device fabricated in our laboratory are clear and show a good triplexing function.

Heteroepitaxial Growth of 3C-SiC Films on Maskless Patterned Silicon Substrates

Heteroepitaxial growth of 3C-SiC on patterned Si substrates by low pressure chemical vapor deposition (LPCVD) has been investigated to improve the crystal quality of 3C-SiC films. Si substrates were patterned with parallel lines, 1 to 10μm wide and spaced 1 to 10μm apart, which was carried out by photolithography and reactive ion etching. Growth behavior on the patterned substrates was systematically studied by scanning electron microscopy (SEM). An air gap structure and a spherical shape were formed on the patterned Si substrates with different dimensions. The air gap formed after coalescence reduced the stress in the 3C-SiC films, solving the wafer warp and making it possible to grow thicker films. XRD patterns indicated that the films grown on the maskless patterned Si substrates were mainly composed of crystal planes with (111) orientation.

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS. While varying geometrical parameters such as the number of turns （N）,the width of the metal traces （W）,the spacing between the traces （S）,and the inner diameter （ID）, changes in the performance of the inductors are analyzed in detail. The reasons for these changes in performance are presented. Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout. Some design rules are summarized.

Low-Microwave Loss Coplanar Waveguides Fabricated on High-Resistivity Silicon Substrate

Three kinds of coplanar waveguides （CPWs） are designed and fabricated on different silicon substrates---common low-resistivity silicon substrate （LRS）, LRS with a 3μm-thick silicon oxide interlayer, and high-resistivity silicon （HRS） substrate. The results show that the microwave loss of a CPW on LRS is too high to be used, but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the LRS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0-26GHz and the process is simple,so HRS is a more suitable CPW substrate.

Design and numerical analysis for low birefringence silica on silicon waveguides

A new fabrication technology for three-dimensionally buried silica on silicon optical waveguide based on deep etching and thermal oxidation is presented. Using this method, a silicon layer is left at the side of waveguide. The stress distribution and effective refractive index are calculated by using finite element method and finite different beam propagation method, respectively. The results indicate that the stress of silica on silicon optical waveguide fabricated by this method can be matched in parallel and vertical directions and stress birefringence can be effectively reduced due to the side-silicon layer.