Measurement-based Method for Wind Farm Power System Oscillations Monitoring

The global increase in the penetration of renewable energy is pushing electrical power systems into uncharted territory, especially in terms of transient and dynamic stability. In particular, the greater penetration of wind generation in European power networks is, at times, displacing a significant capacity of conventional synchronous generation with fixed-speed induction generation and now more commonly, doubly fed induction generators. The impact of such changes in the generation mix requires careful monitoring to assess the impact on transient and dynamic stability. This study presents a measurement-based method for the early detection of power system oscillations, with consideration of mode damping, in order to raise alarms and develop strategies to actively improve power system dynamic stability and security. A method is developed based on wavelet-based support vector data description (SVDD) to detect oscillation modes in wind farm output power, which may excite dynamic instabilities in the wider system. The wavelet transform is used as a filter to identify oscillations in frequency bands, whereas the SVDD method is used to extract dominant features from different scales and generate an assessment boundary according to the extracted features. Poorly damped oscillations of a large magnitude, or that are resonant, can be alarmed to the system operator, to reduce the risk of system instability. The proposed method is exemplified using measured data from a chosen wind farm site.

A Wavelet-Prony Method for Modeling of Fixed-Speed Wind Farm Low-Frequency Power Pulsations

The increasing penetration of wind generation on the Island of Ireland has been accompanied by close investigation of low-frequency pulsations contained within active power flow. A primary concern is excitation of low-frequency oscillation modes already present on the system, particularly the 0.75 Hz mode as a consequence of interconnection between the Northern and Southern power system networks. In order to determine whether the prevalence of wind generation has a negative effect (excites modes) or positive impact (damping of modes) on the power system, oscillations must be measured and characterised. Using time – frequency methods, this paper presents work that has been conducted to extract features from low-frequency active power pulsations to determine the composition of oscillatory modes which may impact on dynamic stability. The paper proposes a combined wavelet-Prony method to extract modal components and determine damping factors. The method is exemplified using real data obtained from wind farm measurements.

Rapid confirmatory method for the determination of sixteen synthetic growth promoters and bisphenol A in bovine milk using dispersive solid-phase extraction and liquid chromatography-tandem mass spectrometry

A rapid liquid chromatographic-tandem mass spectrometric (LC-MS/MS) multi-residue method for the simultaneous quantitation and identification of sixteen synthetic growth promoters and bisphenol A in bovine milk has been developed and validated. Sample preparation was straightforward, efficient and economically advantageous. Milk was extracted with acetonitrile followed by phase separation with NaCl. After centrifugation, the extract was purified by dispersive solid-phase extraction with C18 sorbent material. The compounds were analysed by reversed-phase LC-MS/MS using both positive and negative ionization and operated in multiple reaction monitoring (MRM) mode, acquiring two diagnostic product ions from each of the chosen precursor ions for unambiguous confirmation. Total chromatographic run time was less than 10 min for each sample. The method was validated at a level of 1 mu g L-1. A wide variety of deuterated internal standards were used to improve method performance. The accuracy and precision of the method were satisfactory for all analytes. The confirmative quantitative liquid chromatographic tandem mass spectrometric (LC-MS/MS) method was validated according to Commission Decision 2002/657/EC. The decision limit (CC alpha) and the detection capability (CC beta) were found to be below the chosen validation level of 1 mu g L-1 for all compounds. (C) 2010 Elsevier B.V. All rights reserved.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.