Calculation of engine parameters using reconfigurable hardware

The feasibility of real-time calculation of parameters for an internal combustion engine via reconfigurable hardware implementation is investigated as an alternative to software computation. A detailed in-hardware field programmable gate array (FPGA)-based design is developed and evaluated using input crank angle and in-cylinder pressure data from fully instrumented diesel engines in the QUT Biofuel Engine Research Facility (BERF). Results indicate the feasibility of employing a hardware-based implementation for real-time processing for speeds comparable to the data sampling rate currently used in the facility, with acceptably low level of discrepancies between hardware and software-based calculation of key engine parameters.

Accurate pattern prediction of very closely spaced mismatched antennas using measured active element patterns

A method for prediction of the radiation pattern of N strongly coupled antennas with mismatched sources is presented. The method facilitates fast and accurate design of compact arrays. The prediction is based on the measured N-port S parameters of the coupled antennas and the N active element patterns measured in a 50 ω environment. By introducing equivalent power sources, the radiation pattern with excitation by sources with arbitrary impedances and various decoupling and matching networks (DMN) can be accurately predicted without the need for additional measurements. Two experiments were carried out for verification: pattern prediction for parasitic antennas with different loads and for antennas with DMN. The difference between measured and predicted patterns was within 1 to 2 dB.

Flexible design of decoupling and matching networks for two strongly coupled antennas

The flexible design of decoupling and matching networks for coupled antennas is introduced. The network includes three parts: circuits for impedance transformation, an element for odd-mode decoupling and conventional matching networks. It is found that all three parts are determined by one parameter of the ABCD matrix of the impedance transformation circuit. Thus a large variety of circuits with different element values can be used for decoupling which relaxes the practical design constraints.

Computation of ECG signal features using MCMC modelling in software and FPGA reconfigurable hardware

Computational optimisation of clinically important electrocardiogram signal features, within a single heart beat, using a Markov-chain Monte Carlo (MCMC) method is undertaken. A detailed, efficient data-driven software implementation of an MCMC algorithm has been shown. Initially software parallelisation is explored and has been shown that despite the large amount of model parameter inter-dependency that parallelisation is possible. Also, an initial reconfigurable hardware approach is explored for future applicability to real-time computation on a portable ECG device, under continuous extended use.

3D reconfigurable autopilot flight system for both general aviation and unmanned aerial systems

This research project investigated and designed a modular architecture for a 3D Reconfigurable Autopilot Flight System that could be used to control actuators in both manned and unmanned aircraft. The system is based on a CAN Bus interface and allows seamless control of different types of actuators. During the course of the research the differences and similarities of autopilots for fixed-wing general aviation aircraft and unmanned aircraft were analysed focusing on the actuator interfaces. This project suggests that software and hardware used in commercial-of-the-shelf avionics could be used in manned and unmanned aviation.

Formation of highly conductive composite coatings and their applications to broadband antennas and mechanical transducers

Tight networks of interwoven carbon nanotube bundles are formed in our highly conductive composite. The composite possesses propertiessuggesting a two-dimensional percolative network rather than other reported dispersions displaying three-dimensional networks. Binding nanotubes into large but tight bundles dramatically alters the morphology and electronic transport dynamics of the composite. This enables itto carry higher levels of charge in the macroscale leading to conductivities as high as 1600 S/cm. We now discuss in further detail, the electronic and physical properties of the nanotube composites through Raman spectroscopy and transmission electron microscopy analysis. When controlled and usedappropriately, the interesting properties of these composites reveal their potential for practical device applications. For instance, we used this composite to fabricate coatings, whic improve the properties of an electromagnetic antenna/amplifier transducer. The resulting transducer possesses a broadband range up to GHz frequencies. A strain gauge transducer was also fabricated using changes in conductivity to monitor structural deformations in the composite coatings.

Analysis and design of beam-shaped rectangular polyrod antennas

Theoretical and experimental investigations on the near field and radiation characteristics show a fairly good agreement which justifies the TE(11)(x) mode of excitation. Eight polyrod antennas of different configurations were built and tested as functions of taper angles, straight and curved axial lengths, and frequency of excitation. It is found that the radiation patterns. cross-polarization level, beamwidth and gain could be controlled not only by the axial length and taper angles but also by shaping the axis of the polyrods in order to realize an optimum design

Design of multi-frequency microstrip antennas using multiple rings

An electromagnetically coupled feed arrangement is proposed for simultaneously exciting multiple concentric ring antennas for multi-frequency operation. This has a multi-layer dielectric configuration in which a transmission line is embedded below the layer containing radiating rings. Energy coupled to these rings from the line beneath is optimised by suitably adjusting the location and dimensions of stubs on the line. It has been shown that the resonant frequencies of these rings do not change as several of these single-frequency antennas are combined to form a multi-resonant antenna. Furthermore, all radiators are forced to operate at their primary mode and some harmonics of the lower resonant frequency rings appearing within the frequency range are suppressed when combined. The experimental prototype antenna has three resonant frequencies at which it has good radiation characteristics.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Dual-frequency characteristics of Minkowski-square ring antennas

Fractal Minkowski curves to design a compact dual-frequency microstrip ring antenna are proposed. Sides of a square ring have been selectively replaced with first and second iterations of the generalised fractal geometry to design a smaller antenna with dual-frequency operation. This behaviour has been explained based on current distributions on the antenna structure. Measured results compare well with electromagnetic simulations.

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

A design procedure for micromachined antennas on semiconductor substrates

Micromachined antennas are recieving great interest as carrier frequencies move higher into the frequency spectrum due to their superior performance and amenability for integration with active devices. However their design is cumbersome owing to the complexity of the structure. To overcome this, in this paper, an iterative procedure is suggested to facilitate fast design of micromachined patch antennas based on a simulation study. A microstrip line on a micromachined Silicon substrate is simulated in a full wave simulator by solving for the ports only. From the obtained propagation constant, the effective dilectric constant for the micromachined substrate is estimated. The process is repeated for a number of values of the width of the microstrip and a plot is made for the variation of the effective dielectric constant with the microstrip width. Then an iterative method in combination with the extrapolated permittivity which includes the effect of cavity extensions in all the directions, is used to obtain the width and the corresponding effective dielectric constant. This method has been verified to be quite accurate by comparison with full wave simulations and hence it can function as a good starting point for designers to design micromachined antennas.

High-Rate,2-Group ML-Decodable STBCs for 2(m) Transmit Antennas

A Space-Time Block Code (STBC) in K-variables is said to be g-Group ML-Decodable (GMLD) if its Maximum-Likelihood (ML) decoding metric can be written as a sum of g independent terms, with each term being a function of a subset of the K variables. In this paper, a construction method to obtain high-rate, 2-GMLD STBCs for 2(m) transmit antennas, m > 1, is presented. The rate of the STBC obtained for 2(m) transmit antennas is 2(m-2) + 1/2(m), complex symbols per channel use. The design method is illustrated for the case of 4 and 8 transmit antennas. The code obtained for 4 transmit antennas is equivalent to the rate-5/4 Quasi-Orthogonal design (QOD) proposed by Yuen, Guan and Tjung.