Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

Influence of Band Non-Parabolicity on Few Ballistic Properties of III-V Quantum Wire Field Effect Transistors Under Strong Inversion

A simplified yet analytical approach on few ballistic properties of III-V quantum wire transistor has been presented by considering the band non-parabolicity of the electrons in accordance with Kane's energy band model using the Bohr-Sommerfeld's technique. The confinement of the electrons in the vertical and lateral directions are modeled by an infinite triangular and square well potentials respectively, giving rise to a two dimensional electron confinement. It has been shown that the quantum gate capacitance, the drain currents and the channel conductance in such systems are oscillatory functions of the applied gate and drain voltages at the strong inversion regime. The formation of subbands due to the electrical and structural quantization leads to the discreetness in the characteristics of such 1D ballistic transistors. A comparison has also been sought out between the self-consistent solution of the Poisson's-Schrodinger's equations using numerical techniques and analytical results using Bohr-Sommerfeld's method. The results as derived in this paper for all the energy band models gets simplified to the well known results under certain limiting conditions which forms the mathematical compatibility of our generalized theoretical formalism.

Application of lateral photovoltage towards contactless light beam induced current measurements and its dependence on the finite beam size

The nature of the signal due to light beam induced current (LBIC) at the remote contacts is verified as a lateral photovoltage for non-uniformly illuminated planar p-n junction devices; simulation and experimental results are presented. The limitations imposed by the ohmic contacts are successfully overcome by the introduction of capacitively coupled remote contacts, which yield similar results without any significant loss in the estimated material and device parameters. It is observed that the LBIC measurements introduce artefacts such as shift in peak position with increasing laser power. Simulation of LBIC signal as a function of characteristic length L-c of photo-generated carriers and for different beam diameters has resulted in the observed peak shifts, thus attributed to the finite size of the beam. Further, the idea of capacitively coupled contacts has been extended to contactless measurements using pressure contacts with an oxidized aluminium electrodes. This technique avoids the contagious sample processing steps, which may introduce unintentional defects and contaminants into the material and devices under observation. Thus, we present here, the remote contact LBIC as a practically non-destructive tool in the evaluation of device parameters and welcome its use during fabrication steps. (C) 2014 AIP Publishing LLC.

On the Geometrically Dependent Quasi-Saturation and g(m) Reduction in Advanced DeMOS Transistors

This paper reveals an early quasi-saturation (QS) effect attributed to the geometrical parameters in shallow trench isolation-type drain-extended MOS (STI-DeMOS) transistors in advanced CMOS technologies. The quasi-saturation effect leads to serious g(m) reduction in STI-DeMOS. This paper investigates the nonlinear resistive behavior of the drain-extended region and its impact on the particular behavior of the STI-DeMOS transistor. In difference to vertical DMOS or lateral DMOS structures, STI-DeMOS exhibits three distinct regions of the drain extension. A complete understanding of the physics in these regions and their impact on the QS behavior are developed in this paper. An optimization strategy is shown for an improved g(m) device in a state-of-the-art 28-nm CMOS technology node.

Early Functional Deficit and Microglial Disturbances in a Mouse Model of Amyotrophic Lateral Sclerosis

11 p.

I. Fundamental limitations in microelectronics. II. Power Schottky diode design and comparison with the junction diode. III. Permittivity of strontium titanate

Part I

The physical phenomena which will ultimately limit the packing density of planar bipolar and MOS integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum size of a bipolar transistor is determined by junction breakdown, punch-through and doping fluctuations. The minimum size of a MOS transistor is determined by gate oxide breakdown and drain-source punch-through. The packing density of fully active bipolar or static non-complementary MOS circuits becomes limited by power dissipation. The packing density of circuits which are not fully active such as read-only memories, becomes limited by the area occupied by the devices, and the frequency is limited by the circuit time constants and by metal migration. The packing density of fully active dynamic or complementary MOS circuits is limited by the area occupied by the devices, and the frequency is limited by power dissipation and metal migration. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.

Part II

Because the Schottky diode is a one-carrier device, it has both advantages and disadvantages with respect to the junction diode which is a two-carrier device. The advantage is that there are practically no excess minority carriers which must be swept out before the diode blocks current in the reverse direction, i.e. a much faster recovery time. The disadvantage of the Schottky diode is that for a high voltage device it is not possible to use conductivity modulation as in the p i n diode; since charge carriers are of one sign, no charge cancellation can occur and current becomes space charge limited. The Schottky diode design is developed in Section 2 and the characteristics of an optimally designed silicon Schottky diode are summarized in Fig. 9. Design criteria and quantitative comparison of junction and Schottky diodes is given in Table 1 and Fig. 10. Although somewhat approximate, the treatment allows a systematic quantitative comparison of the devices for any given application.

Part III

We interpret measurements of permittivity of perovskite strontium titanate as a function of orientation, temperature, electric field and frequency performed by Dr. Richard Neville. The free energy of the crystal is calculated as a function of polarization. The Curie-Weiss law and the LST relation are verified. A generalized LST relation is used to calculate the permittivity of strontium titanate from zero to optic frequencies. Two active optic modes are important. The lower frequency mode is attributed mainly to motion of the strontium ions with respect to the rest of the lattice, while the higher frequency active mode is attributed to motion of the titanium ions with respect to the oxygen lattice. An anomalous resonance which multi-domain strontium titanate crystals exhibit below 65°K is described and a plausible mechanism which explains the phenomenon is presented.

p-MOS controlled lateral thyristor: A MOS controllable thyristor suitable for integration

A novel CMOS compatible lateral thyristor is proposed in this paper. Its thyristor conduction is fully controlled by a p-MOS gate. Loss of MOS control due to parasitic latch-up has been eliminated and triggering of the main thyristor at lower forward current achieved. The device operation has been verified by 2-D numerical simulations and experimental fabrication.

Direct growth of horizontally aligned carbon nanotubes between electrodes and its application to field-effect transistors

This paper presents direct growth of horizontally aligned carbon nanotubes (CNTs) between two predefined various inter-spacing up to tens of microns of electrodes (pads) and its use as CNT field-effect transistors (CNT-FETs). The catalytic metals were prepared, consisting of iron (Fe), aluminum (Al) and platinum (Pt) triple layers, on the thermal silicon oxide substrate (Pt/Al/Fe/SiO2). Scanning electron microscopy measurements of CNT-FETs from the as-grown samples showed that over 80% of the nanotubes are grown across the catalytic electrodes. Moreover, the number of CNTs across the catalytic electrodes is roughly controllable by adjusting the growth condition. The Al, as the upper layer on Fe electrode, not only plays a role as a barrier to prevent vertical growth but also serves as a porous medium that helps in forming smaller nano-sized Fe particles which would be necessary for lateral growth of CNTs. Back-gate field effect transistors were demonstrated with the laterally aligned CNTs. The on/off ratios in all the measured devices are lower than 100 due to the drain leakage current. ©2010 IEEE.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.