Low-cost hardware speech enhancement for improved speech recognition in automotive environments

Voice recognition is one of the key enablers to reduce driver distraction as in-vehicle systems become more and more complex. With the integration of voice recognition in vehicles, safety and usability are improved as the driver’s eyes and hands are not required to operate system controls. Whilst speaker independent voice recognition is well developed, performance in high noise environments (e.g. vehicles) is still limited. La Trobe University and Queensland University of Technology have developed a low-cost hardware-based speech enhancement system for automotive environments based on spectral subtraction and delay–sum beamforming techniques. The enhancement algorithms have been optimised using authentic Australian English collected under typical driving conditions. Performance tests conducted using speech data collected under variety of vehicle noise conditions demonstrate a word recognition rate improvement in the order of 10% or more under the noisiest conditions. Currently developed to a proof of concept stage there is potential for even greater performance improvement.

Development of an online condition monitoring system for slow speed machinery

One of the main challenges of slow speed machinery condition monitoring is that the energy generated from an incipient defect is too weak to be detected by traditional vibration measurements due to its low impact energy. Acoustic emission (AE) measurement is an alternative for this as it has the ability to detect crack initiations or rubbing between moving surfaces. However, AE measurement requires high sampling frequency and consequently huge amount of data are obtained to be processed. It also requires expensive hardware to capture those data, storage and involves signal processing techniques to retrieve valuable information on the state of the machine. AE signal has been utilised for early detection of defects in bearings and gears. This paper presents an online condition monitoring (CM) system for slow speed machinery, which attempts to overcome those challenges. The system incorporates relevant signal processing techniques for slow speed CM which include noise removal techniques to enhance the signal-to-noise and peak-holding down sampling to reduce the burden of massive data handling. The analysis software works under Labview environment, which enables online remote control of data acquisition, real-time analysis, offline analysis and diagnostic trending. The system has been fully implemented on a site machine and contributing significantly to improve the maintenance efficiency and provide a safer and reliable operation.

Development of an autonomous unmanned aerial system to collect time-stamped samples from the atmosphere and localize potential pathogen sources

This paper presents the hardware development and testing of a new concept for air sampling via the integration of a prototype spore trap onboard an unmanned aerial system (UAS).We propose the integration of a prototype spore trap onboard a UAS to allow multiple capture of spores of pathogens in single remote locations at high or low altitude, otherwise not possible with stationary sampling devices.We also demonstrate the capability of this system for the capture of multiple time-stamped samples during a single mission.Wind tunnel testing was followed by simulation, and flight testing was conducted to measure and quantify the spread during simulated airborne air sampling operations. During autonomous operations, the onboard autopilot commands the servo to rotate the sampling device to a new indexed location once the UAS vehicle reaches the predefined waypoint or set of waypoints (which represents the region of interest). Time-stamped UAS data are continuously logged during the flight to assist with analysis of the particles collected. Testing and validation of the autopilot and spore trap integration, functionality, and performance is described. These tools may enhance the ability to detect new incursions of spores

A hardware virtualization-based component sandboxing architecture

Modern applications comprise multiple components, such as browser plug-ins, often of unknown provenance and quality. Statistics show that failure of such components accounts for a high percentage of software faults. Enabling isolation of such fine-grained components is therefore necessary to increase the robustness and resilience of security-critical and safety-critical computer systems. In this paper, we evaluate whether such fine-grained components can be sandboxed through the use of the hardware virtualization support available in modern Intel and AMD processors. We compare the performance and functionality of such an approach to two previous software based approaches. The results demonstrate that hardware isolation minimizes the difficulties encountered with software based approaches, while also reducing the size of the trusted computing base, thus increasing confidence in the solution's correctness. We also show that our relatively simple implementation has equivalent run-time performance, with overheads of less than 34%, does not require custom tool chains and provides enhanced functionality over software-only approaches, confirming that hardware virtualization technology is a viable mechanism for fine-grained component isolation.

Studies in power hardware in the loop (PHIL) simulation using real-time digital simulator (RTDS)

In power hardware in the loop (PHIL) simulations, a real-time simulated power system is interfaced to a piece of hardware, usually called hardware under test (HuT). A PHIL test can be realized using several simulation tools. Among them Real Time Digital Simulator (RTDS) is an ideal tool to perform complex power system simulations in near real-time. Stable operation of the entire system, along with the accuracy of simulation results are the main concerns regarding a PHIL simulation. In this paper, a simulated power network on RTDS will be interfaced to HuT through a voltage source converter (VSC). Issues around stability and other interface problems are studied and a new method to stabilize some unstable PHIL cases is proposed. PHIL simulation results in PSCAD and RSCAD are presented.

System level tests of transformer differential protection using an IEC 61850 process bus

The IEC 61850 family of standards for substation communication systems were released in the early 2000s, and include IEC 61850-8-1 and IEC 61850-9-2 that enable Ethernet to be used for process-level connections between transmission substation switchyards and control rooms. This paper presents an investigation of process bus protection performance, as the in-service behavior of multi-function process buses is largely unknown. An experimental approach was adopted that used a Real Time Digital Simulator and 'live' substation automation devices. The effect of sampling synchronization error and network traffic on transformer differential protection performance was assessed and compared to conventional hard-wired connections. Ethernet was used for all sampled value measurements, circuit breaker tripping, transformer tap-changer position reports and Precision Time Protocol synchronization of sampled value merging unit sampling. Test results showed that the protection relay under investigation operated correctly with process bus network traffic approaching 100% capacity. The protection system was not adversely affected by synchronizing errors significantly larger than the standards permit, suggesting these requirements may be overly conservative. This 'closed loop' approach, using substation automation hardware, validated the operation of protection relays under extreme conditions. Digital connections using a single shared Ethernet network outperformed conventional hard-wired solutions.

Comparison of high level FPGA hardware design for solving tri-diagonal linear systems

Reconfigurable computing devices can increase the performance of compute intensive algorithms by implementing application specific co-processor architectures. The power cost for this performance gain is often an order of magnitude less than that of modern CPUs and GPUs. Exploiting the potential of reconfigurable devices such as Field-Programmable Gate Arrays (FPGAs) is typically a complex and tedious hardware engineering task. Re- cently the major FPGA vendors (Altera, and Xilinx) have released their own high-level design tools, which have great potential for rapid development of FPGA based custom accelerators. In this paper, we will evaluate Altera’s OpenCL Software Development Kit, and Xilinx’s Vivado High Level Sythesis tool. These tools will be compared for their per- formance, logic utilisation, and ease of development for the test case of a Tri-diagonal linear system solver.

Consultant engagement for computer system selection: a pro-active client role in small enterprises

Because of their limited number of senior positions and fewer alternative career paths, small businesses have a more difficult time attracting and retaining skilled information systems (IS) staff and are thus dependent upon external expertise. Small businesses are particularly dependent on outside expertise when first computerizing. Because small businesses suffer from severe financial constraints. it is often difficult to justify the cost of custom software. Hence. for many small businesses, engaging a consultant to help with identifying suitable packaged software and related hardware, is their first critical step toward computerization. This study explores the importance of proactive client involvement when engaging a consultant to assist with computer system selection in small businesses. Client involvement throughout consultant engagement is found to be integral to project success and frequently lacking due to misconceptions of small businesses regarding their role. Small businesses often overestimate the impact of consultant and vendor support in achieving successful computer system selection and implementation. For consultant engagement to be successful, the process must be viewed as being directed toward the achievement of specific organizational results where the client accepts responsibility for direction of the process.

A Cyber-Physical System Simulator for risk-free transport studies

The article introduces a novel platform for conducting controlled and risk-free driving and traveling behavior studies, called Cyber-Physical System Simulator (CPSS). The key features of CPSS are: (1) simulation of multiuser immersive driving in a threedimensional (3D) virtual environment; (2) integration of traffic and communication simulators with human driving based on dedicated middleware; and (3) accessibility of multiuser driving simulator on popular software and hardware platforms. This combination of features allows us to easily collect large-scale data on interesting phenomena regarding the interaction between multiple user drivers, which is not possible with current single-user driving simulators. The core original contribution of this article is threefold: (1) we introduce a multiuser driving simulator based on DiVE, our original massively multiuser networked 3D virtual environment; (2) we introduce OpenV2X, a middleware for simulating vehicle-to-vehicle and vehicle to infrastructure communication; and (3) we present two experiments based on our CPSS platform. The first experiment investigates the “rubbernecking” phenomenon, where a platoon of four user drivers experiences an accident in the oncoming direction of traffic. Second, we report on a pilot study about the effectiveness of a Cooperative Intelligent Transport Systems advisory system.

Privacy enhancements for hardware-based security modules

The increasing growth in the use of Hardware Security Modules (HSMs) towards identification and authentication of a security endpoint have raised numerous privacy and security concerns. HSMs have the ability to tie a system or an object, along with its users to the physical world. However, this enables tracking of the user and/or an object associated with the HSM. Current systems do not adequately address the privacy needs and as such are susceptible to various attacks. In this work, we analyse various security and privacy concerns that arise when deploying such hardware security modules and propose a system that allow users to create pseudonyms from a trusted master public-secret key pair. The proposed system is based on the intractability of factoring and finding square roots of a quadratic residue modulo a composite number, where the composite number is a product of two large primes. Along with the standard notion of protecting privacy of an user, the proposed system offers colligation between seemingly independent pseudonyms. This new property when combined with HSMs that store the master secret key is extremely beneficial to a user, as it offers a convenient way to generate a large number of pseudonyms using relatively small storage requirements.

Controlling current and voltage type interfaces in power-hardware-in-the-loop simulations

The usual practice to study a large power system is through digital computer simulation. However, the impact of large scale use of small distributed generators on a power network cannot be evaluated strictly by simulation since many of these components cannot be accurately modelled. Moreover, the network complexity makes the task of practical testing on a physical network nearly impossible. This study discusses the paradigm of interfacing a real-time simulation of a power system to real-life hardware devices. This type of splitting a network into two parts and running a real-time simulation with a physical system in parallel is usually termed as power-hardware-in-the-loop (PHIL) simulation. The hardware part is driven by a voltage source converter that amplifies the signals of the simulator. In this paper, the effects of suitable control strategy on the performance of PHIL and the associated stability aspects are analysed in detail. The analyses are validated through several experimental tests using an real-time digital simulator.

Stability synthesis of power hardware-in-the-loop (PHIL) simulation

A virtual power system can be interfaced with a physical system to form a power hardware-in-the-loop (PHIL) simulation. In this scheme, the virtual system can be simulated in a fast parallel processor to provide near real-time outputs, which then can be interfaced to a physical hardware that is called the hardware under test (HuT). Stable operation of the entire system, while maintaining acceptable accuracy, is the main challenge of a PHIL simulation. In this paper, after an extended stability analysis for voltage and current type interfaces, some guidelines are provided to have a stable PHIL simulation. The presented analysis have been evaluated by performing several experimental tests using a Real Time Digital Simulator (RTDS™) and a voltage source converter (VSC). The practical test results are consistent with the proposed analysis.

System design for a small autonomous helicopter

The detailed system design of a small experimental autonomous helicopter is described. The system requires no ground-to-helicopter communications and hence all automation hardware is on-board the helicopter. All elements of the system are described including the control computer, the flight computer (the helicopter-to-control-computer interface), the sensors and the software. A number of critical implementation issues are also discussed.

3D reconfigurable autopilot flight system for both general aviation and unmanned aerial systems

This research project investigated and designed a modular architecture for a 3D Reconfigurable Autopilot Flight System that could be used to control actuators in both manned and unmanned aircraft. The system is based on a CAN Bus interface and allows seamless control of different types of actuators. During the course of the research the differences and similarities of autopilots for fixed-wing general aviation aircraft and unmanned aircraft were analysed focusing on the actuator interfaces. This project suggests that software and hardware used in commercial-of-the-shelf avionics could be used in manned and unmanned aviation.

The dual nature of information systems in enabling a new wave of hardware ventures: Towards a theory

Hardware ventures are emerging entrepreneurial firms that create new market offerings based on development of digital devices. These ventures are important elements in the global economy but have not yet received much attention in the literature. Our interest in examining hardware ventures is specifically in the role that information system (IS) resources play in enabling them. We ask how the role of IS resources for hardware ventures can be conceptualized and develop a framework for assessment. Our framework builds on the distinction of operand and operant resources and distinguishes between two key lifecycle stages of hardware ventures: start-up and growth. We show how this framework can be used to discuss the role, nature, and use of IS for hardware ventures and outline empirical research strategies that flow from it. Our work contributes to broadening and enriching the IS field by drawing attention to its role in significant and novel phenomena.