EEG seizure in bilateral ECT is different between low and high stimulus doses

Melancholic depressive patients referred for ECT were randomized to receive either low dose (n = 20) or high dose (n = 20) stimulus applied bifrontotemporally. The two stimulus groups were comparable on the clinical variables. The EEG seizure was recorded on two channels (right and left frontal), digitized, coded and analyzed offline without knowledge of ECT parameters. EEG seizure was of comparable duration in the two stimulus (high dose and low dose) groups. A new composite measure, Strength-Symmetry-Index (SSI), based on strength and symmetry of seizure EEG was computed using fractal geometry. The SSI of the early-seizure was higher in the high dose than in the low dose ECT group. In a stepwise, logistic regression model, this variable contributed to 65% with correct classification of high dose and low dose ECT seizures.

Implementation of Art1 and Art2 Artificial Neural Networks on Ring and Mesh Architectures

The Artificial Neural Networks (ANNs) are being used to solve a variety of problems in pattern recognition, robotic control, VLSI CAD and other areas. In most of these applications, a speedy response from the ANNs is imperative. However, ANNs comprise a large number of artificial neurons, and a massive interconnection network among them. Hence, implementation of these ANNs involves execution of computer-intensive operations. The usage of multiprocessor systems therefore becomes necessary. In this article, we have presented the implementation of ART1 and ART2 ANNs on ring and mesh architectures. The overall system design and implementation aspects are presented. The performance of the algorithm on ring, 2-dimensional mesh and n-dimensional mesh topologies is presented. The parallel algorithm presented for implementation of ART1 is not specific to any particular architecture. The parallel algorithm for ARTE is more suitable for a ring architecture.

Equivalent Circuit Analysis of Serpentine Folded-waveguide Slow-wave Structures for Millimeter-wave Traveling-wave Tubes

A simple equivalent circuit model for the analysis of dispersion and interaction impedance characteristics of serpentine folded-waveguide slow-wave structure was developed by considering the straight and curved portions of structure supporting the dominant TE10-mode of the rectangular waveguide. Expressions for the lumped capacitance and inductance per period of the slow-wave structure were derived in terms of the physical dimensions of the structure, incorporating the effects of the beam-hole in the lumped parameters. The lumped parameters were subsequently interpreted for obtaining the dispersion and interaction impedance characteristics of the structure. The analysis was simple yet accurate in predicting the dispersion and interaction impedance behaviour at millimeter-wave frequencies. The analysis was benchmarked against measurement as well as with 3D electromagnetic modeling using MAFIA for two typical slow-wave structures (one at the Ka-band and the other at the W-band) and close agreement observed.

Analysis of Rectangular Folded-Waveguide Millimeter-Wave Slow-wave Structures using Conformal Transformations

An analysis of rectangular folded-waveguide slow-wave structure was developed using conformal mapping technique through Schwarz's polygon transformation and closed form expressions for the lumped capacitance and inductance per period of the slow-wave structure were derived in terms of the physical dimensions of the structure, incorporating the effects of the beam hole in the lumped parameters. The lumped parameters were subsequently interpreted for obtaining the dispersion and interaction impedance characteristics of the structure. The analysis was benchmarked for two typical millimeter-wave structures, one operating in Ka-band and the other operating in Q-band, against measurement and 3D electromagnetic modeling using MAFIA.

Analytical approximation solutions for 3-D optical waveguides: Review

The rectangular dielectric waveguide is the most commonly used structure in integrated optics, especially in semi-conductor diode lasers. Demands for new applications such as high-speed data backplanes in integrated electronics, waveguide filters, optical multiplexers and optical switches are driving technology toward better materials and processing techniques for planar waveguide structures. The infinite slab and circular waveguides that we know are not practical for use on a substrate because the slab waveguide has no lateral confinement and the circular fiber is not compatible with the planar processing technology being used to make planar structures. The rectangular waveguide is the natural structure. In this review, we have discussed several analytical methods for analyzing the mode structure of rectangular structures, beginning with a wave analysis based on the pioneering work of Marcatili. We study three basic techniques with examples to compare their performance levels. These are the analytical approach developed by Marcatili, the perturbation techniques, which improve on the analytical solutions and the effective index method with examples.

Energy-Efficient Decentralized Cooperative Routing in Wireless Networks

Wireless adhoc networks transmit information from a source to a destination via multiple hops in order to save energy and, thus, increase the lifetime of battery-operated nodes. The energy savings can be especially significant in cooperative transmission schemes, where several nodes cooperate during one hop to forward the information to the next node along a route to the destination. Finding the best multi-hop transmission policy in such a network which determines nodes that are involved in each hop, is a very important problem, but also a very difficult one especially when the physical wireless channel behavior is to be accounted for and exploited. We model the above optimization problem for randomly fading channels as a decentralized control problem - the channel observations available at each node define the information structure, while the control policy is defined by the power and phase of the signal transmitted by each node. In particular, we consider the problem of computing an energy-optimal cooperative transmission scheme in a wireless network for two different channel fading models: (i) slow fading channels, where the channel gains of the links remain the same for a large number of transmissions, and (ii) fast fading channels, where the channel gains of the links change quickly from one transmission to another. For slow fading, we consider a factored class of policies (corresponding to local cooperation between nodes), and show that the computation of an optimal policy in this class is equivalent to a shortest path computation on an induced graph, whose edge costs can be computed in a decentralized manner using only locally available channel state information (CSI). For fast fading, both CSI acquisition and data transmission consume energy. Hence, we need to jointly optimize over both these; we cast this optimization problem as a large stochastic optimization problem. We then jointly optimize over a set of CSI functions of the local channel states, and a c- - orresponding factored class of control poli.

Linear filtering in DCT IV/DST IV and MDCT/MDST domain

In this paper, expressions for convolution multiplication properties of DCT IV and DST IV are derived starting from equivalent DFT representations. Using these expressions methods for implementing linear filtering through block convolution in the DCT IV and DST IV domain are proposed. Techniques developed for DCT IV and DST IV are further extended to MDCT and MDST where the filter implementation is near exact for symmetric filters and approximate for non-symmetric filters. No additional overlapping is required for implementing the symmetric filtering in the MDCT domain and hence the proposed algorithm is computationally competitive with DFT based systems. Moreover, inherent 50% overlap between the adjacent frames used for MDCT/MDST domain reduces the blocking artifacts due to block processing or quantization. The techniques are computationally efficient for symmetric filters and provides a new alternative to DFT based convolution.

Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Broadband Suspended Microstrip Antenna For Circular Polarization

In this paper we propose a circularly polarized (CP) microstrip antenna on a suspended substrate with a coplanar capacitive feed and a slot within the rectangular patch. The antenna has an axial ratio bandwidth (< 3 dB) of 7.1%. The proposed antenna exhibits a much higher impedance bandwidth of about 49% (S11 < -10 dB) and also yields return loss better than -15 dB in the useful range of circular polarization. Measured characteristics of the antenna are in good agreement with the simulated results. The radiation patterns indicate good cross polarization rejection and low back lobe radiations. The design proposed here can be scaled to any frequency of interest.

On-Chip Clock Network Skew Measurement using Sub-Sampling

We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

Co-ordinate Interleaved Distributed Space-Time Coding for Two-Antenna-Relays Networks

Distributed space time coding for wireless relay networks when the source, the destination and the relays have multiple antennas have been studied by Jing and Hassibi. In this set-up, the transmit and the receive signals at different antennas of the same relay are processed and designed independently, even though the antennas are colocated. In this paper, a wireless relay network with single antenna at the source and the destination and two antennas at each of the R relays is considered. A new class of distributed space time block codes called Co-ordinate Interleaved Distributed Space-Time Codes (CIDSTC) are introduced where, in the first phase, the source transmits a T-length complex vector to all the relays;and in the second phase, at each relay, the in-phase and quadrature component vectors of the received complex vectors at the two antennas are interleaved and processed before forwarding them to the destination. Compared to the scheme proposed by Jing-Hassibi, for T >= 4R, while providing the same asymptotic diversity order of 2R, CIDSTC scheme is shown to provide asymptotic coding gain with the cost of negligible increase in the processing complexity at the relays. However, for moderate and large values of P, CIDSTC scheme is shown to provide more diversity than that of the scheme proposed by Jing-Hassibi. CIDSTCs are shown to be fully diverse provided the information symbols take value from an appropriate multidimensional signal set.

Novel schmitt trigger based on lahbda diode

A new circuit to realise a Schmitt trigger has been conceived. This circuit, which is based on the well known lambda diode, is suitable for integration using CMOS technology. It requires only three devices and is probably simpler than any other conventional Schmitt trigger circuit.

Fast Multiple Access Selection through variable power transmissions

Many wireless applications demand a fast mechanism to detect the packet from a node with the highest priority ("best node") only, while packets from nodes with lower priority are irrelevant. In this paper, we introduce an extremely fast contention-based multiple access algorithm that selects the best node and requires only local information of the priorities of the nodes. The algorithm, which we call Variable Power Multiple Access Selection (VP-MAS), uses the local channel state information from the accessing nodes to the receiver, and maps the priorities onto the receive power. It is based on a key result that shows that mapping onto a set of discrete receive power levels is optimal, when the power levels are chosen to exploit packet capture that inherently occurs in a wireless physical layer. The VP-MAS algorithm adjusts the expected number of users that contend in each step and their respective transmission powers, depending on whether previous transmission attempts resulted in capture, idle channel, or collision. We also show how reliable information regarding the total received power at the receiver can be used to improve the algorithm by enhancing the feedback mechanism. The algorithm detects the packet from the best node in 1.5 to 2.1 slots, which is considerably lower than the 2.43 slot average achieved by the best algorithm known to date.

Carrier mobility in polycrystalline semiconductors

This letter presents a modified version of the grain boundary barrier model for polycrystalline semiconductors which takes into account the carrier transport in the bulk of the grain and the dynamic process of capture and release of free carriers by the grain boundary traps.

Fault tolerance in multiprocessor systems

Multiprocessor systems which afford a high degree of parallelism are used in a variety of applications. The extremely stringent reliability requirement has made the provision of fault-tolerance an important aspect in the design of such systems. This paper presents a review of the various approaches towards tolerating hardware faults in multiprocessor systems. It. emphasizes the basic concepts of fault tolerant design and the various problems to be taken care of by the designer. An indepth survey of the various models, techniques and methods for fault diagnosis is given. Further, we consider the strategies for fault-tolerance in specialized multiprocessor architectures which have the ability of dynamic reconfiguration and are suited to VLSI implementation. An analysis of the state-óf-the-art is given which points out the major aspects of fault-tolerance in such architectures.