On-Chip Clock Network Skew Measurement using Sub-Sampling
| Data(s) |
03/11/2008
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|---|---|
| Resumo |
We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps. |
| Formato |
application/pdf |
| Identificador |
http://eprints.iisc.ernet.in/20012/1/mrs.pdf Das, Pratap Kumar and Bharadwaj, Amrutur and Sridhar, J and Visvanathan, V (2008) On-Chip Clock Network Skew Measurement using Sub-Sampling. In: 4th IEEE Asian Solid-State Circuits Conference, NOV 03-05, 2008, Fukuoka, Japan. |
| Publicador |
IEEE |
| Relação |
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4708812&tag=1 http://eprints.iisc.ernet.in/20012/ |
| Palavras-Chave | #Electrical Communication Engineering |
| Tipo |
Conference Paper PeerReviewed |
