(Table 1) Os and Sr isotopes in low-temperature hydrothermal fluids from the Juan de Fuca Ridge at ODP Site 168-1026B

We present Os and Sr isotopes and Mg, Os, and Sr concentrations for ridge-crest high-temperature and diffuse hydrothermal fluids, plume fluids and ridge-flank warm spring fluids from the Juan de Fuca Ridge. The data are used to evaluate the extent to which (1) the high- and low-temperature hydrothermal alteration of mid-ocean ridge basalts (MORBs) provides Os to the deep oceans, and (2) hydrothermal contributions of non-radiogenic Os and Sr to the oceans are coupled. The Os and Sr isotopic ratios of the high-temperature fluids (265-353°C) are dominated by basalts (187Os/188Os = 0.2; 87Sr/86Sr = 0.704) but the concentrations of these elements are buffered approximately at their seawater values. The 187Os/188Os of the hydrothermal plume fluids collected ~1 m above the orifice of Hulk vent is close to the seawater value (=1.05). The low-temperature diffuse fluids (10-40°C) associated with ridge-crest high-temperature hydrothermal systems on average have [Os] = 31 fmol/kg, 187Os/188Os = 0.9 and [Sr] = 86 µmol/kg, 87Sr/86Sr = 0.709. They appear to result from mixing of a high-temperature fluid and a seawater component. The ridge-flank warm spring fluids (10-62°C) on average yield [Os] = 22 fmol/kg, 187Os/188Os = 0.8 and [Sr] = 115 µmol/kg, 87Sr/86Sr = 0.708. The data are consistent with isotopic exchange of Os and Sr between basalt and circulating seawater during low-temperature hydrothermal alteration. The average Sr concentration in these fluids appears to be similar to seawater and consistent with previous studies. In comparison, the average Os concentration is less than seawater by more than a factor of two. If these data are representative they indicate that low-temperature alteration of MORB does not provide adequate non-radiogenic Os and that another source of mantle Os to the oceans must be investigated. At present, the magnitude of non-radiogenic Sr contribution via low-temperature seawater alteration is not well constrained. If non-radiogenic Sr to the oceans is predominantly from the alteration of MORB, our data suggest that there must be a different source of non-radiogenic Os and that the Os and Sr isotope systems in the oceans are decoupled.

In Situ effects of low pH and elevated HCO3 on juvenile massive Porites spp. in Moorea, French Polynesia

Juvenile colonies of massive Porites spp. were exposed to manipulated pH and bicarbonate ([HCO3-]) in situ to test the hypothesis that ocean acidification (OA) does not affect respiration and calcification. Incubations lasted 28 h and exposed corals to ambient temperature and light with ecologically relevant water motion. Three treatments were applied: (1) ambient conditions of pH 8.04 and 1751 µmol HCO3- kg(-1) (Treatment 1), (2) pCO2-induced ocean acidification of pH 7.73 and 2011 µmol HCO3- kg(-1) (Treatment 2), and (3) pCO2 and HCO3--enriched seawater of pH 7.69 and 2730 µmol HCO3- kg(-1) (Treatment 3). The third treatment providing elevated [HCO3-] was used to test for stimulatory effects of dissolved inorganic carbon on calcification under low pH and low saturation of aragonite (Omega arag), but it does not reflect conditions expected to occur under CO2-driven OA. Calcification of juvenile massive Porites spp. was affected by treatments, with an 81% elevation in Treatment 3 versus Treatment 1, but no difference between Treatments 1 and 2; respiration and the metabolic expenditure concurrent with calcification remained unaffected. These findings indicate that juvenile massive Porites spp. are resistant to short exposures to OA in situ, and separately, that they can increase calcification at low pH and low Omega arag if [HCO3-] is elevated. Juvenile Porites spp. may therefore be limited by dissolved inorganic carbon under ambient pCO2 conditions

Enhanced iron gettering by short, optimized low-temperature annealing after phosphorus emitter diffusion for industrial silicon solar cell processing

The introduction of a low-temperature (LT) tail after P emitter diffusion was shown to lead to considerable improvements in electron lifetime and solar cell performance by different researchers. So far, the drawback of the investigated extended gettering treatments has been the lack of knowledge about optimum annealing times and temperatures and the important increase in processing time. In this manuscript, we calculate optimum annealing temperatures of Fe-contaminated Si wafers for different annealing durations. Subsequently, it is shown theoretically and experimentally that a relatively short LT tail of 15 min can lead to a significant reduction of interstitial Fe and an increase in electron lifetime. Finally, we calculate the potential improvement of solar cell efficiency when such a short-tail extended P diffusion gettering is included in an industrial fabrication process.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Invariance of the Glass Transition Temperature of Plant Vitrification Solutions with Cooling Rate

The solutions studied were Plant Vitrification Solutions 1, 2 and 3: (PVS1: Uragami et al. 1989, Plant Cell Rep. 8, 418; PVS2: Sakai et al. 1990, Plant Cell Rep. 9, 30; PVS3: Nishizawa et al. 1993, Plant Sci. 91, 67). Cooling was performed using the calorimeter control (5, 10 and 20°C min-1), or for higher rates, by quenching the closed pan with PVS in LN, either naked (faster - 5580°C min-1) or introduced in cryovials (reduced rate 360°C min-1). Quenched pans were then transferred to the sample chamber, pre-cooled to -196°C. Glass transition temperature was observed by DSC with a TA 2920 instrument, upon warming pans with solution samples from -145°C to room temperature, at standard warming rate10°C min-1.

Laminar-turbulent transition induced by a discrete roughness element in a supersonic boundary layer

The linear instability and breakdown to turbulence induced by an isolated roughness element in a boundary layer at Mach 2:5, over an isothermal flat plate with laminar adiabatic wall temperature, have been analysed by means of direct numerical simulations, aided by spatial BiGlobal and three-dimensional parabolized (PSE-3D) stability analyses. It is important to understand transition in this flow regime since the process can be slower than in incompressible flow and is crucial to prediction of local heat loads on next-generation flight vehicles. The results show that the roughness element, with a height of the order of the boundary layer displacement thickness, generates a highly unstable wake, which is composed of a low-velocity streak surrounded by a three-dimensional high-shear layer and is able to sustain the rapid growth of a number of instability modes. The most unstable of these modes are associated with varicose or sinuous deformations of the low-velocity streak; they are a consequence of the instability developing in the three-dimensional shear layer as a whole (the varicose mode) or in the lateral shear layers (the sinuous mode). The most unstable wake mode is of the varicose type and grows on average 17% faster tan the most unstable sinuous mode and 30 times faster than the most unstable boundary layer mode occurring in the absence of a roughness element. Due to the high growthrates registered in the presence of the roughness element, an amplification factor of N D 9 is reached within 50 roughness heights from the roughness trailing edge. The independently performed Navier–Stokes, spatial BiGlobal and PSE-3D stability results are in excellent agreement with each other, validating the use of simplified theories for roughness-induced transition involving wake instabilities. Following the linear stages of the laminar–turbulent transition process, the roll-up of the three-dimensional shear layer leads to the formation of a wedge of turbulence, which spreads laterally at a rate similar to that observed in the case of compressible turbulent spots for the same Mach number.

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.

Mechanical behavior and deformation micromechanisms of polypropylene nonwoven fabrics as a function of temperature and strain rate

The mechanical behavior and the deformation and failure micromechanisms of a thermally-bonded polypropylene nonwoven fabric were studied as a function of temperature and strain rate. Mechanical tests were carried out from 248 K (below the glass transition temperature) up to 383 K at strain rates in the range ≈10−3 s−1 to 10−1 s−1. In addition, individual fibers extracted from the nonwoven fabric were tested under the same conditions. Micromechanisms of deformation and failure at the fiber level were ascertained by means of mechanical tests within the scanning electron microscope while the strain distribution at the macroscopic level upon loading was determined by means of digital image correlation. It was found that the nonwoven behavior was mainly controlled by the properties of the fibers and of the interfiber bonds. Fiber properties determined the nonlinear behavior before the peak load while the interfiber bonds controlled the localization of damage after the peak load. The influence of these properties on the strength, ductility and energy absorbed during deformation is discussed from the experimental observations.

High Intensity Low Temperature (HILT) performance of space concentrator GaInP/GaInAs/Ge MJ SCs

In the work, the results of an investigation of GaInP/GaInAs/Ge MJ SCs intended for converting concentrated solar radiation, when operating at low temperatures (down to -190 degrees C) are presented. A kink of the cell I-V characteristic has been observed in the region close to V-oc starting from -20 degrees C at operation under concentrated sunlight. The causes for its occurrence have been analyzed and the reasons for formation of a built-in potential barrier for majority charge carriers at the n-GaInP/n-Ge isotype hetero-interface are discussed. The effect of charge carrier transport in n-GaInP/n-p Ge heterostructures on MJ SC output characteristics at low temperatures has been studied including EL technique.

A novel high-sensitivity, low-power, liquid crystal temperature sensor

A novel temperature sensor based on nematic liquid crystal permittivity as a sensing magnitude, is presented. This sensor consists of a specific micrometric structure that gives considerable advantages from other previous related liquid crystal (LC) sensors. The analytical study reveals that permittivity change with temperature is introduced in a hyperbolic cosine function, increasing the sensitivity term considerably. The experimental data has been obtained for ranges from −6 °C to 100 °C. Despite this, following the LC datasheet, theoretical ranges from −40 °C to 109 °C could be achieved. These results have revealed maximum sensitivities of 33 mVrms/°C for certain temperature ranges; three times more than of most silicon temperature sensors. As it was predicted by the analytical study, the micrometric size of the proposed structure produces a high output voltage. Moreover the voltage’s sensitivity to temperature response can be controlled by the applied voltage. This response allows temperature measurements to be carried out without any amplification or conditioning circuitry, with very low power consumption.

Low-temperature concentration of tellurium and gold in continental red bed successions

Acknowledgements This research was supported by NERC grants (NE/L001764/1, NE/M010953/1). We are grateful to J. Still and A. Sandison for technical support and to the gypsum mines and C. Brolley for access and sampling. Critical comments from Cristiana Ciobanu, Eric Gloaguen and Georges Calas are gratefully acknowledged. The authors have no conflicts of interest to declare

In vitro selection of self-cleaving RNAs with a low pH optimum

RNAs that undergo a rapid site-specific cleavage at low pH have been selected by in vitro selection (the SELEX process). The cleavage does not require the addition of any divalent metal ions, and is in fact inhibited by divalent metal ions, spermine, or high concentrations of monovalent metal ions. This low pH catalyzed cleavage results in a 2′,3′-cyclic phosphate at the 3′ end and a free hydroxyl at the 5′ end. The reaction proceeds with a calculated rate of 1.1 min−1 at room temperature in cacodylate buffer at pH 5.0. The rate of cleavage is dependent on the pH and shows an optimum around pH 4.0. The rate constant is independent of RNA concentration, indicating to an intramolecular reaction. Autocatalytic cleavage at low pH, in the absence of a metal ion requirement, adds to the reaction possibilities that may have existed on the prebiotic earth.