A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

Radiation response of partially-depleted MOS transistors fabricated in the fluorinated SIMOX wafers

Ionizing radiation response of partially-depleted MOS transistors fabricated in the, fluorinated SIMOX wafers has been investigated. The experimental data show that the, radiation-induced threshold voltage shift of PMOSFETs and NMOSFETs, as well as the radiation-induced increase of off-state leakage current of NMOSFETs can be restrained by implanting fluorine ions into the buried oxide of SIMOX wafers.

Methane hydrate growth velocity in seepage system of Qiongdongnan Basin, South China Sea

The occurrences of diapirs, gas-filled zones and gas plumes in seawater in Qiongdongnan Basin of South China Sea indicate that there may exist seepage system gas-hydrate reservoirs. Assuming there has a methane venting zone of 1500 m in diameter, and the methane flux is 1000 kmol/a, and the temperature of methane hydrate-bearing sediments ranges from 3 degrees C to 20 degrees C, then according to the hydrate film growth theory, by numerical simulation, this paper computes the temperatures and velocities in 0 mbsf, 100 mbsf, 200 mbsf, 425 mbsf over discrete length, and gives the change charts. The results show that the cementation velocity in sediments matrix of methane hydrate is about 0.2 nm/s, and the seepage system will evolve into diffusion system over probably 35000 years. Meanwhile, the methane hydrate growth velocity in leakage system is 20 similar to 40 times faster than in diffusion system.

Temperature-stimulated abnormal annealing of neutron-induced damage in high-resistivity silicon detectors

Neutron-irradiated high-resistivity silicon detectors have been subjected to elevated temperature annealing (ETA). It has been found that both detector full depletion voltage and leakage current exhibit abnormal annealing (or ''reverse annealing'') behaviour for highly irradiated detectors: increase with ETA. Laser induced current measurements indicate a net increase of acceptor type space charges associated with the full depletion voltage increase after ETA. Current deep level transient spectroscopy (I-DLTS) and thermally stimulated current (TSC) data show that the dominant effect is the increase of a level at 0.39 eV below the conduction band (E(c) - 0.39 eV) or a level above the valence band (E(v) + 0.39 eV). Candidates tentatively identified for this level are the singly charged double vacancy (V-V-) level at E(c) - 0.39 eV, the carbon interstitial-oxygen interstitial (C-i-O-i) level at E(v) + 0.36 eV, and/or the tri-vacancy-oxygen center (V3O) at E(v) + 0.40 eV.

Investigation on the N-eff reverse annealing effect using TSC/I-DLTS: Relationship between neutron induced microscopic defects and silicon detector electrical degradations

Neutron induced defect levels in high resistivity silicon detectors have been studied using a current-based macroscopic defect analysis system: thermally stimulated current (TSC) and current deep level transient spectroscopy (I-DLTS). These studies have been correlated to the traditional C-V, I-V, and transient current and charge techniques (TCT/TChT) after neutron radiation and subsequent thermal anneals. It has been found that the increases of the space charge density, N-eff, in irradiated detectors after thermal anneals (N-eff reverse anneal) correspond to the increases of deep levels in the silicon bandgap. In particular, increases of the double vacancy center (V-V and V-V-- -) and/or C-i-O-i level have good correlations with the N-eff reverse anneal. It has also been observed that the leakage current of highly irradiated (Phi(n) > 10(13) n/cm(2)) detectors increases after thermal anneals, which is different from the leakage current annealing behavior of slightly irradiated (Phi(n) < 10(13) n/cm(2)) detectors. It is apparent that V-V center and/or C-i-O-i level play important roles in both N-eff and leakage current degradations for highly irradiated high resistivity silicon detectors.

Microscopic analysis of defects in a high resistivity silicon detector irradiated to 1.7x10(15)n/cm(2)

Current-based microscopic defect analysis methods with optical filling techniques, namely current deep level transient spectroscopy (I-DLTS) and thermally stimulated current (TSC), have been used to study defect levels in a high resistivity silicon detector (p(+)-n-n(+)) induced by very high fluence neutron (VHFN) irradiation (1.7x10(15) n/cm(2)). As many as fourteen deep levels have been detected by I-DLTS. Arrhenius plots of the I-DLTS data have shown defects with energy levels ranging from 0.03 eV to 0.5 eV in the energy band gap. Defect concentrations of relatively shallow levels (E(t) < 0.33 eV) are in the order of 10(13)cm(-3), while those for relatively deep levels (E(t) > 0.33 eV) are in the order of 10(14) cm(-3). TSC data have shown similar defect spectra. A full depletion voltage of about 27,000 volts has been estimated by C-V measurements for the as-irradiated detector, which corresponds to an effective space charge density (N-eff) in the order of 2x10(14) cm(-3). Both detector leakage current and full depletion voltage have been observed to increase with elevated temperature annealing (ETA). The increase of the full depletion voltage corresponds to the increase of some deep levels, especially the 0.39 eV level. Results of positron annihilation spectroscopy have shown a decrease of total concentration of vacancy related defects including vacancy clusters with ETA, suggesting the breaking up of vacancy clusters as possible source of vacancies for the formation of single defects during the reverse anneal.

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dBc/Hz@1MHz.The reference spur is -52 dBc.

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.

Total Dose Radiation-Hard 0. SOI CMOS Transistors and ASIC

This paper presents the total dose radiation performance of 0. S^m SOI CMOS devices fabricated with full dose SIMOX technology. The radiation performance is characterized by threshold voltage shifts and leakage currents of transistors and standby currents of ASIC as functions of the total dose up to 500krad(Si) .The experimental results show that the worst case threshold voltage shifts of front channels are less than 320mV for pMOS transistors under off-gate radiation bias at lMrad(Si) and less than 120mV for nMOS transistors under on-gate radiation bias. No significant radiation-induced leakage current is observed in transistors to lMrad(Si). The standby currents of ASIC are less than the specification of 5μA over the total dose range of 500krad(Si).

Ti Schottky barrier diodes on n-type 6H-SiC

Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes (SBD) were fabricated. They showed good rectification characteristics from room temperature to 200degreesC. At low current density. the current conduction mechanism follows the thermionic emission theory. These diodes demonstrated a low reverse leakage current of below 1 X 10(-4)Acm(-2). Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800V. In addition. these SBDs showed superior switching characteristics.

JFET SOS devices: Processing and gamma radiation effects

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

Improvement of CMOS SOS devices characteristics by a modified solid phase epitaxy

CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

Visible vertical cavity surface emitting laser

We have designed and fabricated the visible vertical-cavity surface-emitting lasers (VCSEL's) by using metalorganic vapor phase epitaxy (MOVPE). We use the 8 lambda optical cavities with 3 quantum wells in AlGaInP/AlGaAs red VCSEL's to reduce the drift leakage current and enhance the model gain in AlGaInP active region. The structure has a p-type stack with 36 DBR pairs on the top and an n-type with 55-1/2 pairs on the bottom. Using micro-area reflectance spectrum, we try to get a better concordance between the center wavelength of DBR and the emitting wavelength of the active region. We used a component graded layer of 0.05 lambda thick (x = 0.5 similar to 0.9) at the p-type DBR AlGaAs/AlAs interface to reduce the resistance of p-type DBR. We use selective oxidation to define the current injection path. Because the oxidation rate of a thick layer is faster than a thinner one, we grown a thick AlAs layer close to the active region. In this way, we got a smaller active region for efficient confinement of injected carriers (the aperture area is 3 x 3 mu m) to reduce the threshold and, at the same time, a bigger conductive area in the DBR layers to reduce the resistance. We employ Zn doping on the p-side of the junction to improve hole injection and control the Zn dopant diffusion to get proper p-i-n junction. At room temperature, pulse operation of the laser has been achieved with the low threshold current of 0.8mA; the wavelength is about 670nm.

Applications of dielectric thin film by electron cyclotron resonance plasma chemical vapor deposition for semiconductor photoelectronic devices

The paper reports a method of depositing SiO2, SiNx, a:Si, Si3N4 and SiOxNy dielectric thin films by electron cyclotron resonance plasma chemical vapor deposition (ECR CVD) on InP, InGaAs and other compound semiconductor optoelectronic devices,and give a technology of depositing dielectric thin films and optical coatings by ECR CVD on Laser's Bars. The experiment results show the dielectric thin films and optical coatings are stable at thermomechanical property,optical properties and the other properties. In addition, the dielectric thin film deposition that there is low leakage current is reported for using as diffusion and ion implatation masks in the paper. In the finally, the dielectric film refractive index can be accurately controlled by the N-2/O-2/Ar gas flow rate.

Temperature dependence of photoluminescence of flat and undulated SiGe/Si multiple quantum wells

Photoluminescence (PL) of strained SiGe/Si multiple quantum wells (MQW) with flat and undulated SiGe well layers was studied at different temperature. With elevated temperature from 10K, the no-phonon (NP) peak of the SiGe layers in the flat sample has firstly a blue shift due to the dominant transition converting from bound excitons (BE) to free excitons (FE), and then has a red shift when the temperature is higher than 30K because of the narrowing of the band gap. In the undulated sample, however, monotonous blue shift was observed as the temperature was elevated from 10 K to 287 K. The thermally activated electrons, confined in Si due to type-II band alignment, leak into the SiGe crest regions, and the leakage is enhanced with the elevated temperature. It results in a blue shift of the SiGe luminescence spectra.