面向红外、紫外焦平面阵列的读出电路的研究

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硅基光波导化学传感器研究

研究了基于硅基集成光波导的马赫-曾德干涉仪(MZI)型化学传感芯片的设计、制备及相关敏感特性的模拟和分析.传感芯片采用硅基二氧化硅光波导材料,利用与传统互补型金属氧化物半导体(CMOS)兼容的工艺技术制作.通过波导的单模设计以及对MZI结构的优化,获得了有效折射率分辨率达到10~(-7)量级的高灵敏度传感芯片.作为化学传感器,把MZI的其中一臂设计成传感臂.并进行适当的表面修饰,可制作出高灵敏度的干涉型光波导化学传感器.最后,对该传感器的折射率分辨率、敏感特性等进行了分析、模拟,同时,对面临的关键问题进行了分析和讨论.

片上集成自动可调谐非对称带通滤波器

提出了具有3阶高通、2阶低通的带有自动调谐系统的有源电阻电容非对称带通滤波器结构.带通滤波器的中心频率为4.055 MHz,带宽为2.63 MHz.源阻抗为50Ω时,滤波器带内3阶交凋量为18.489 dB·m.滤波器输人参考噪声为47.91×10~(-6)V_(rms)(均方根电压).滤波器采用基于二进制搜索算法(BSA)的调谐方案,其调谐精度为(-1.65%,2.66%).调谐电路的芯片面积为0.282 mm×0.204 mm,不到主滤波器面积的1/5.调谐系统完成调谐功能后会自动关闭,降低了功耗和对主滤波器的串扰.在1.8 V电源电压下,滤波器消耗电流为1.96 mA.该滤波器已在IBM 0.18 μm标准互补金属氧化物半导体(CMOS)工艺线流片成功.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

一种带有精准调谐结构的有源RC低通滤波器的设计

提出了一种带有精准调谐结构的有源RC低通滤波器的设计方案,其截止频率为5MHz,并在0.18μm标准CMOS工艺线上流片得到验证.调谐精度达到(-1.24%,+2.16%),测试中得到验证.调谐系统所占芯片面积仅为主滤波器面积的1/4.调谐系统完成调谐功能后会自动关闭,降低了功耗以及对主滤波器的串扰.以50Ω作为源阻抗,滤波器带内3阶交调量(IIP3)好于16.1dBm.滤波器输入参考噪声为36μVrms.滤波器群延迟时间波动测试结果为24ns.滤波器功耗为3.6mW.带有这种调谐结构的滤波器容易被实现,可以用于很多无线低中频应用中,例如全球定位系统、全球通和码分多址等芯片系统中.

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD, we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.

硅基光电子学研究进展与趋势

近年来硅基光电子材料和器件受到高度的重视.利用外延生长和键合技术成功研制出硅基应变赝衬底、GexSi1-x/Si量子阱、高密度锗量子点、硅基InGaAsP/Si异质结,这些进展为硅基光电子器件提供了坚实的材料基础.同CMOS工艺相结合,实现了硅量子点1.17 μm的受激发射,研制出硅基Raman激光器、1.55 μm混合型激光器、高灵敏度的Si/Ge探测器、谐振腔增强型的SiGe光电二极管、调制频率30 GHz的SOI CMOS光学调制器和16×16的SOI光开关阵列等.硅光电子学将在光通信、光计算等领域获得重要应用.本文综述了国内外硅基光电子材料和器件的进展、我们的研究结果和硅基光电子学的发展趋势.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×10~(11) rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.

SOI纳米线波导和相关器件研究进展

SOI纳米线波导具有对光场限制作用强、传输损耗低、弯曲半径小、集成度高、与传统CMOS工艺兼容等优点,采用SOI纳米线波导能够大大缩小光子器件的长度和面积,提高器件工作速度和效率,降低器件功耗.介绍了SOI纳米线波导在模式、损耗、偏振等方面与传统大尺寸硅基波导所表现出来的不同特性,评述了当前关于SOI纳米线波导和基于SOI纳米线波导光子器件的最新研究进展.

一种新型的5GHz自适应偏置及可变增益低噪声放大器

该文提出了一种新型的自适应偏置及可变增益低噪声放大器（LNA），利用电荷泵（亦称电压倍增器）将LNA输出信号转换成与LNA射频输入信号功率成比例变化的直流信号，以此信号同时反馈控制LNA的偏置和增益，来实现自适应偏置以及可变增益低噪声放大器。从而极大地改善了LNA的输入线性范围。鉴于5GHz频率下，Bipolar相对于CMOS更好的频率特性和低噪声特性，该项研究采用了BiCMOS工艺，实现了低于3．0dB的噪声系数（高增益状态下）和大约13dBm的输入三阶交调点ⅡP3的控制范围以及大于15dB的增益控制范围。