RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

Semi-supervised learning of WLAN radio maps

In this thesis a manifold learning method is applied to the problem of WLAN positioning and automatic radio map creation. Due to the nature of WLAN signal strength measurements, a signal map created from raw measurements results in non-linear distance relations between measurement points. These signal strength vectors reside in a high-dimensioned coordinate system. With the help of the so called Isomap-algorithm the dimensionality of this map can be reduced, and thus more easily processed. By embedding position-labeled strategic key points, we can automatically adjust the mapping to match the surveyed environment. The environment is thus learned in a semi-supervised way; gathering training points and embedding them in a two-dimensional manifold gives us a rough mapping of the measured environment. After a calibration phase, where the labeled key points in the training data are used to associate coordinates in the manifold representation with geographical locations, we can perform positioning using the adjusted map. This can be achieved through a traditional supervised learning process, which in our case is a simple nearest neighbors matching of a sampled signal strength vector. We deployed this system in two locations in the Kumpula campus in Helsinki, Finland. Results indicate that positioning based on the learned radio map can achieve good accuracy, especially in hallways or other areas in the environment where the WLAN signal is constrained by obstacles such as walls.

Future chemistry teachers use of knowledge dimensions and high-order cognitive skills in pre-laboratory concept maps

This poster describes a pilot case study, which aim is to study how future chemistry teachers use knowledge dimensions and high-order cognitive skills (HOCS) in their pre-laboratory concept maps to support chemistry laboratory work. The research data consisted of 168 pre-laboratory concept maps that 29 students constructed as a part of their chemistry laboratory studies. Concept maps were analyzed by using a theory based content analysis through Anderson & Krathwohls' learning taxonomy (2001). This study implicates that novice concept mapper students use all knowledge dimensions and applying, analyzing and evaluating HOCS to support the pre-laboratory work.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Enhancement of workability in AZ31 alloy-processing maps: Part I,castmaterial

Processing maps developed on the basis of the Dynamic Materials Model provide valuable information that might help the metal working industry in solving problems related to workability and microstructural control in commercial alloys. In this research, the processing maps for an as-cast AZ31 magnesium alloy are presented. The results are validated via microstructural observations, clearly delineating safe and unsafe regimes for further process design of this alloy.

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

High temperature deformation processing maps for boron modified Ti-6Al-4V alloys

The alloy, Ti-6Al-4V is an alpha + beta Ti alloy that has large prior beta grain size (similar to 2 mm) in the as cast state. Minor addition of B (about 0.1 wt.%) to it refines the grain size significantly as well as produces in-situ TiB needles. The role played by these microstructural modifications on high temperature deformation processing maps of B-modified Ti64 alloys is examined in this paper.Power dissipation efficiency and instability maps have been generated within the temperature range of 750-1000 degrees C and strain rate range of 10(-3)-10(+1) s(-1). Various deformation mechanisms, which operate in different temperature-strain rate regimes, were identified with the aid of the maps and complementary microstructural analysis of the deformed specimens. Results indicate four distinct deformation domains within the range of experimental conditions examined, with the combination of 900-1000 degrees C and 10(-3)-10(-2) s(-1) being the optimum for hot working. In that zone, dynamic globularization of alpha laths is the principle deformation mechanism. The marked reduction in the prior beta grain size, achieved with the addition of B, does not appear to alter this domain markedly. The other domains, with negative values of instability parameter, show undesirable microstructural features such as extensive kinking/bending of alpha laths and breaking of beta laths for Ti64-0.0B as well as generation of voids and cracks in the matrix and TiB needles in the B-modified alloys. (C) 2010 Elsevier B.V. All rights reserved.

Constructing Reeb Graphs using Cylinder Maps

The Reeb graph of a scalar function represents the evolution of the topology of its level sets. In this video, we describe a near-optimal output-sensitive algorithm for computing the Reeb graph of scalar functions defined over manifolds. Key to the simplicity and efficiency of the algorithm is an alternate definition of the Reeb graph that considers equivalence classes of level sets instead of individual level sets. The algorithm works in two steps. The first step locates all critical points of the function in the domain. Arcs in the Reeb graph are computed in the second step using a simple search procedure that works on a small subset of the domain that corresponds to a pair of critical points. The algorithm is also able to handle non-manifold domains.

Design of Single-Input-Single-Output Compliant Mechanisms for Practical Applications Using Selection Maps

We present an interactive map-based technique for designing single-input-single-output compliant mechanisms that meet the requirements of practical applications. Our map juxtaposes user-specifications with the attributes of real compliant mechanisms stored in a database so that not only the practical feasibility of the specifications can be discerned quickly but also modifications can be done interactively to the existing compliant mechanisms. The practical utility of the method presented here exceeds that of shape and size optimizations because it accounts for manufacturing considerations, stress limits, and material selection. The premise for the method is the spring-leverage (SL) model, which characterizes the kinematic and elastostatic behavior of compliant mechanisms with only three SL constants. The user-specifications are met interactively using the beam-based 2D models of compliant mechanisms by changing their attributes such as: (i) overall size in two planar orthogonal directions, separately and together, (ii) uniform resizing of the in-plane widths of all the beam elements, (iii) uniform resizing of the out-of-plane thick-nesses of the beam elements, and (iv) the material. We present a design software program with a graphical user interface for interactive design. A case-study that describes the design procedure in detail is also presented while additional case-studies are posted on a website. DOI:10.1115/1.4001877].

Root system traits of Norway spruce, Scots pine, and silver birch in mixed boreal forests: an analysis of root architecture, morphology, and anatomy

The aim of this thesis was to unravel the functional-structural characteristics of root systems of Betula pendula Roth., Picea abies (L.) Karst., and Pinus sylvestris L. in mixed boreal forest stands differing in their developmental stage and site fertility. The root systems of these species had similar structural regularities: horizontally-oriented shallow roots defined the horizontal area of influence, and within this area, each species placed fine roots in the uppermost soil layers, while sinker roots defined the maximum rooting depth. Large radial spread and high ramification of coarse roots, and the high specific root length (SRL) and root length density (RLD) of fine roots indicated the high belowground competitiveness and root plasticity of B. pendula. Smaller radial root spread and sparser branching of coarse roots, and low SRL and RLD of fine roots of the conifers could indicate their more conservative resource use and high association with and dependence on ectomycorrhiza-forming fungi. The vertical fine root distributions of the species were mostly overlapping, implying the possibility for intense belowground competition for nutrients. In each species, conduits tapered and their frequency increased from distal roots to the stem, from the stem to the branches, and to leaf petioles in B. pendula. Conduit tapering was organ-specific in each species violating the assumptions of the general vascular scaling model (WBE). This reflects the hierarchical organization of a tree and differences between organs in the relative importance of transport, safety, and mechanical demands. The applied root model was capable of depicting the mass, length and spread of coarse roots of B. pendula and P. abies, and to the lesser extent in P. sylvestris. The roots did not follow self-similar fractal branching, because the parameter values varied within the root systems. Model parameters indicate differences in rooting behavior, and therefore different ecophysiological adaptations between species.