Development and regeneration of neuronal circuits in the vertebrate retina

Thesis (Ph.D.)--University of Washington, 2016-08

Introduction to the Special Issue on Biomedical and Bioelectronic Circuits for Enhanced Diagnosis and Therapy

The 22 papers in this special issue focus on biomedical and biolectronic circuits for enhanced diagnosis and therapy.

Modulateurs intégrés sur silicium pour la transmission de signaux à modulation d'amplitude multi-niveau

Au cours des dernières années, la photonique intégrée sur silicium a progressé rapidement. Les modulateurs issus de cette technologie présentent des caractéristiques potentiellement intéressantes pour les systèmes de communication à courte portée. En effet, il est prévu que ces modulateurs pourront être opérés à des vitesses de transmission élevées, tout en limitant le coût de fabrication et la consommation de puissance. Parallèlement, la modulation d’amplitude multi-niveau (PAM) est prometteuse pour ce type de systèmes. Ainsi, ce travail porte sur le développement de modulateurs de silicium pour la transmission de signaux PAM. Dans le premier chapitre, les concepts théoriques nécessaires à la conception de modulateurs de silicium sont présentés. Les modulateurs Mach-Zehnder et les modulateurs à base de réseau de Bragg sont principalement abordés. De plus, les effets électro-optiques dans le silicium, la modulation PAM, les différents types d’électrodes intégrées et la compensation des distorsions par traitement du signal sont détaillés.Dans le deuxième chapitre, un modulateur Mach-Zehnder aux électrodes segmentées est présenté. La segmentation des électrodes permet la génération de signaux optiques PAM à partir de séquences binaires. Cette approche permet d’éliminer l’utilisation de convertisseur numérique-analogique en intégrant cette fonction dans le domaine optique, ce qui vise à réduire le coût du système de communication. Ce chapitre contient la description détaillée du modulateur, les résultats de caractérisation optique et de la caractérisation électrique, ainsi que les tests systèmes. De plus, les tests systèmes incluent l’utilisation de pré-compensation ou de post-compensation du signal sous la forme d’égalisation de la réponse en fréquence pour les formats de modulation PAM-4 et PAM-8 à différents taux binaires. Une vitesse de transmission de 30 Gb/s est démontrée dans les deux cas et ce malgré une limitation importante de la réponse en fréquence suite à l’ajout d’un assemblage des circuits radiofréquences (largeur de bande 3 dB de 8 GHz). Il s’agit de la première démonstration de modulation PAM-8 à l’aide d’un modulateur Mach-Zehnder aux électrodes segmentées. Finalement, les conclusions tirées de ce travail ont mené à la conception d’un deuxième modulateur Mach-Zehnder aux électrodes segmentées présentement en phase de test, dont les performances montrent un très grand potentiel. Dans le troisième chapitre, un modulateur à réseau de Bragg à deux sauts de phase est présenté. L’utilisation de réseaux de Bragg est une approche encore peu développée pour la modulation. En effet, la réponse spectrale de ces structures peut être contrôlée précisément, une caractéristique intéressante pour la conception de modulateurs. Dans ces travaux, nous proposons l’ajout de deux sauts de phase à un réseau de Bragg uniforme pour obtenir un pic de transmission dans la bande de réflexion de celui-ci. Ainsi, il est possible d’altérer l’amplitude du pic de transmission à l’aide d’une jonction pn. Comme pour le deuxième chapitre, ce chapitre inclut la description détaillée du modulateur, les résultats des caractérisations optique et électrique, ainsi que les tests systèmes. De plus, la caractérisation de jonctions pn à l’aide du modulateur à réseau de Bragg est expliquée. Des vitesses de transmission PAM-4 de 60 Gb/s et OOK de 55 Gb/s sont démontrées après la compensation des distorsions des signaux. À notre connaissance, il s’agit du modulateur à réseau de Bragg le plus rapide à ce jour. De plus, pour la première fois, les performances d’un tel modulateur s’approchent de celles des modulateurs de silicium les plus rapides utilisant des microrésonateurs en anneau ou des interféromètres Mach-Zehnder.

Modélisation des machines par circuits couplés pour l’observation des courants de barres au rotor

Ce travail présente une modélisation rapide d’ordre élévé capable de modéliser une configuration rotorique en cage complète ou en grille, de reproduire les courants de barre et tenir compte des harmoniques d’espace. Le modèle utilise une approche combinée d’éléments finis avec les circuits-couplés. En effet, le calcul des inductances est réalisé avec les éléments finis, ce qui confère une précision avancée au modèle. Cette méthode offre un gain important en temps de calcul sur les éléments finis pour des simulations transitoires. Deux outils de simulation sont développés, un dans le domaine du temps pour des résolutions dynamiques et un autre dans le domaine des phaseurs dont une application sur des tests de réponse en fréquence à l’arrêt (SSFR) est également présentée. La méthode de construction du modèle est décrite en détail de même que la procédure de modélisation de la cage du rotor. Le modèle est validé par l’étude de machines synchrones: une machine de laboratoire de 5.4 KVA et un grand alternateur de 109 MVA dont les mesures expérimentales sont comparées aux résultats de simulation du modèle pour des essais tels que des tests à vide, des courts-circuits triphasés, biphasés et un test en charge.

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

Photonic integrated circuits development: a universal transceiver for NG-PON2

In the last years there has been a clear evolution in the world of telecommunications, which goes from new services that need higher speeds and higher bandwidth, until a role of interactions between people and machines, named by Internet of Things (IoT). So, the only technology able to follow this growth is the optical communications. Currently the solution that enables to overcome the day-by-day needs, like collaborative job, audio and video communications and share of les is based on Gigabit-capable Passive Optical Network (G-PON) with the recently successor named Next Generation Passive Optical Network Phase 2 (NG-PON2). This technology is based on the multiplexing domain wavelength and due to its characteristics and performance becomes the more advantageous technology. A major focus of optical communications are Photonic Integrated Circuits (PICs). These can include various components into a single device, which simpli es the design of the optical system, reducing space and power consumption, and improves reliability. These characteristics make this type of devices useful for several applications, that justi es the investments in the development of the technology into a very high level of performance and reliability in terms of the building blocks. With the goal to develop the optical networks of future generations, this work presents the design and implementation of a PIC, which is intended to be a universal transceiver for applications for NG-PON2. The same PIC will be able to be used as an Optical Line Terminal (OLT) or an Optical Network Unit (ONU) and in both cases as transmitter and receiver. Initially a study is made of Passive Optical Network (PON) and its standards. Therefore it is done a theoretical overview that explores the materials used in the development and production of this PIC, which foundries are available, and focusing in SMART Photonics, the components used in the development of this chip. For the conceptualization of the project di erent architectures are designed and part of the laser cavity is simulated using Aspic™. Through the analysis of advantages and disadvantages of each one, it is chosen the best to be used in the implementation. Moreover, the architecture of the transceiver is simulated block by block through the VPItransmissionMaker™ and it is demonstrated its operating principle. Finally it is presented the PIC implementation.

Generating a state t-design by diagonal quantum circuits

We investigate protocols for generating a state t-design by using a fixed separable initial state and a diagonal-unitary t-design in the computational basis, which is a t-design of an ensemble of diagonal unitary matrices with random phases as their eigenvalues. We first show that a diagonal-unitary t-design generates a O (1/2(N))-approximate state t-design, where N is the number of qubits. We then discuss a way of improving the degree of approximation by exploiting non-diagonal gates after applying a diagonal-unitary t-design. We also show that it is necessary and sufficient to use O (log(2)(t)) -qubit gates with random phases to generate a diagonal-unitary t-design by diagonal quantum circuits, and that each multi-qubit diagonal gate can be replaced by a sequence of multi-qubit controlled-phase-type gates with discrete-valued random phases. Finally, we analyze the number of gates for implementing a diagonal-unitary t-design by non-diagonal two- and one-qubit gates. Our results provide a concrete application of diagonal quantum circuits in quantum informational tasks.

From Hardware Processes to asynchronous circuits via petri nets: An Application to Arbiter Design

International audience

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Análise e projeto de um conversor boost de três níveis intercalado

This paper presents the development of a boost converter with the possibility of higher gain than the conventional boost converter for applications under similar conditions and increased power. Presents the main concepts involving the boost converter and two variations: the boost converter of three levels and the boost converter interspersed with two converter cells. The breakdown mounting positions, the operating steps, the addressing and the main strengths of each converter in order to check for possible uses in the construction of a prototype joining their main advantages. In the presentation of this converter addresses the operating steps, the equation governing its design, the simulations obtained through software (PSIM), a comparison between the boost converter models studied and the experimental results.

A Methodology for estimating energy consumption of QDI asynchronous circuits

International audience

Improving DPA and DFA resistance of circuits using asynchronous logic

International audience

Quasi delay insensitive asynchronous circuits for low EMI

International audience

Projeto, implementação e análise de um conversor CC-CC de alto ganho e alto rendimento para aplicações fotovoltaicas

In recent years the photovoltaic generation has had greater insertion in the energy mix of the most developed countries, growing at annual rates of over 30%. The pressure for the reduction of pollutant emissions, diversification of the energy mix and the drop in prices are the main factors driving this growth. Grid tied systems plays an important role in alleviating the energy crisis and diversification of energy sources. Among the grid tied systems, building integrated photovoltaic systems suffers from partial shading of the photovoltaic modules and consequently the energy yield is reduced. In such cases, classical forms of modules connection do not produce good results and new techniques have been developed to increase the amount of energy produced by a set of modules. In the parallel connection technique of photovoltaic modules, a high voltage gain DC-DC converter is required, which is relatively complex to build with high efficiency. The current-fed isolated converters explored in this work have some desirable characteristics for this type of application, such as: low input current ripple and input voltage ripple, high voltage gain, galvanic isolation, feature high power capacity and it achieve soft switching in a wide operating range. This study presents contributions to the study of a high gain and high efficiency DC-DC converter for use in a parallel system of photovoltaic generation, being possible the use in a microinverter or with central inverter. The main contributions of this work are: analysis of the active clamping circuit operation proposing that the clamp capacitor connection must be done on the negative node of the power supply to reduce the input current ripple and thus reduce the filter requirements; use of a voltage doubler in the output rectifier to reduce the number of components and to extend the gain of the converter; detailed study of the converter components in order to raise the efficiency; obtaining the AC equivalent model and control system design. As a result, a DC-DC converter with high gain, high efficiency and without electrolytic capacitors in the power stage was developed. In the final part of this work the DC-DC converter operation connected to an inverter is presented. Besides, the DC bus controller is designed and are implemented two maximum power point tracking algorithms. Experimental results of full system operation connected to an emulator and subsequently to a real photovoltaic module are also given.

Components and circuits for tunneling diode based high frequency sources

Terahertz (THz) technology has been generating a lot of interest because of the potential applications for systems working in this frequency range. However, to fully achieve this potential, effective and efficient ways of generating controlled signals in the terahertz range are required. Devices that exhibit negative differential resistance (NDR) in a region of their current-voltage (I-V ) characteristics have been used in circuits for the generation of radio frequency signals. Of all of these NDR devices, resonant tunneling diode (RTD) oscillators, with their ability to oscillate in the THz range are considered as one of the most promising solid-state sources for terahertz signal generation at room temperature. There are however limitations and challenges with these devices, from inherent low output power usually in the range of micro-watts (uW) for RTD oscillators when milli-watts (mW) are desired. At device level, parasitic oscillations caused by the biasing line inductance when the device is biased in the NDR region prevent accurate device characterisation, which in turn prevents device modelling for computer simulations. This thesis describes work on I-V characterisation of tunnel diode (TD) and RTD (fabricated by Dr. Jue Wang) devices, and the radio frequency (RF) characterisation and small signal modelling of RTDs. The thesis also describes the design and measurement of hybrid TD oscillators for higher output power and the design and measurement of a planar Yagi antenna (fabricated by Khalid Alharbi) for THz applications. To enable oscillation free current-voltage characterisation of tunnel diodes, a commonly employed method is the use of a suitable resistor connected across the device to make the total differential resistance in the NDR region positive. However, this approach is not without problems as the value of the resistor has to satisfy certain conditions or else bias oscillations would still be present in the NDR region of the measured I-V characteristics. This method is difficult to use for RTDs which are fabricated on wafer due to the discrepancies in designed and actual resistance values of fabricated resistors using thin film technology. In this work, using pulsed DC rather than static DC measurements during device characterisation were shown to give accurate characteristics in the NDR region without the need for a stabilisation resistor. This approach allows for direct oscillation free characterisation for devices. Experimental results show that the I-V characterisation of tunnel diodes and RTD devices free of bias oscillations in the NDR region can be made. In this work, a new power-combining topology to address the limitations of low output power of TD and RTD oscillators is presented. The design employs the use of two oscillators biased separately, but with the combined output power from both collected at a single load. Compared to previous approaches, this method keeps the frequency of oscillation of the combined oscillators the same as for one of the oscillators. Experimental results with a hybrid circuit using two tunnel diode oscillators compared with a single oscillator design with similar values shows that the coupled oscillators produce double the output RF power of the single oscillator. This topology can be scaled for higher (up to terahertz) frequencies in the future by using RTD oscillators. Finally, a broadband Yagi antenna suitable for wireless communication at terahertz frequencies is presented in this thesis. The return loss of the antenna showed that the bandwidth is larger than the measured range (140-220 GHz). A new method was used to characterise the radiation pattern of the antenna in the E-plane. This was carried out on-wafer and the measured radiation pattern showed good agreement with the simulated pattern. In summary, this work makes important contributions to the accurate characterisation and modelling of TDs and RTDs, circuit-based techniques for power combining of high frequency TD or RTD oscillators, and to antennas suitable for on chip integration with high frequency oscillators.