A Methodology for estimating energy consumption of QDI asynchronous circuits
| Contribuinte(s) |
Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF) - Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP) - Institut National Polytechnique de Grenoble (INPG) - Centre National de la Recherche Scientifique (CNRS) - Université Grenoble Alpes (UGA) |
|---|---|
| Cobertura |
Santorini, Greece |
| Data(s) |
15/09/2004
|
| Resumo |
International audience This paper presents a new methodology for estimating the energy consumption of Quasi Delay Insensitive (QDI) asynchronous circuits. The estimation corresponds to a gate transition count weighted with the gate sizes. The estimation is embedded in the TAST design flow and is done early in the flow, more precisely at the CHP specification in order to supply to the designer useful information of the energy consumption of a circuit. It is performed in two steps: a structural estimation and a dynamic estimation. The usefulness of this estimation for energy optimization is shown through a data encoding example. |
| Identificador |
hal-01392558 |
| Idioma(s) |
fr |
| Publicador |
HAL CCSD Springer |
| Direitos |
http://creativecommons.org/licenses/by-nc/ |
| Fonte |
14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'04) https://hal.archives-ouvertes.fr/hal-01392558 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'04), Sep 2004, Santorini, Grèce. Springer Proceedings |
| Palavras-Chave | #PACS 8542 #[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics |
| Tipo |
info:eu-repo/semantics/conferenceObject Conference papers |
