Organic Thin-Film Transistor Memory With Nanoparticle Floating Gate

Organic thin-film transistor memory devices were realized by inserting a layer of nanoparticles (such as Ag or CaF2) between two Nylon 6 gate dielectrics as the floating gate. The transistor memories were fabricated on glass substrates by full thermal deposition. The transistors exhibit significant hysteresis behavior in current-voltage characteristics, due to the separated Ag or CaF2 nanoparticle islands that act as charge trap centers. The mechanism of the transistor memory operation was discussed.

Micropatterning of metal films coated on polymer surfaces with epoxy mold and its application to organic field effect transistor fabrication

In this letter, a simple and versatile approach to micropatterning a metal film, which is evaporated on a Si substrate coated with polymer, is demonstrated by the use of a prepatterned epoxy mold. The polymer interlayer between the metal and the Si substrate is found important for the high quality pattern. When the metal-polymer-Si sandwich structure is heated with the temperature below T-m but above T-g of the polymer, the plastic deformation of the polymer film occurs under sufficiently high pressure applied. It causes the metal to crack locally or weaken along the pattern edges. Further heating while applying a lower pressure results in the formation of an intimate junction between the epoxy stamp and the metal film. Under these conditions the epoxy cures further, ensuring adhesion between the stamp and the film. The lift-off process works because the adhesion between the epoxy and the metal film is stronger than that between the metal film and the polymer. A polymer field effect transistor is fabricated in order to demonstrate potential applications of this micropatterning approach.

Copper phthalocyanine based hybrid p-type permeable-base transistor in vertical architecture

We demonstrate the production of copper phthalocyanine (CuPc) based p-type hybrid permeable-base transistors, which operate at low voltages having high common-base current gains. These transistors are prepared by evaporating a thin metal layer (Ag or Al) that acts as base on top of a Si substrate that acts as collector. In the sequence CuPc and Au are thermally sublimated to produce the emitter, constituting a quite simple device production procedure with the additional advantage of allowing higher integration due to its vertical architecture.

High current density tris(8-hydroxyquinoline) aluminum-based hybrid transistor in vertical architecture

We report the construction of hybrid permeable-base transistors, in vertical architecture, using tris(8-hydroxyquinoline) aluminum as emitter, a thin gold layer as base, and n-type silicon as collector. These transistors present high common-base current gain, can be operated at low driving voltages, and allow high current density.

A Network Charge-Orineted MOS Transistor Model

The MOS transistor physical model as described in [3] is presented here as a network model. The goal is to obtain an accurate model, suitable for simulation, free from certain problems reported in the literature [13], and conceptually as simple as possible. To achieve this goal the original model had to be extended and modified. The paper presents the derivation of the network model from physical equations, including the corrections which are required for simulation and which compensate for simplifications introduced in the original physical model. Our intrinsic MOS model consists of three nonlinear voltage-controlled capacitors and a dependent current source. The charges of the capacitors and the current of the current source are functions of the voltages $V_{gs}$, $V_{bs}$, and $V_{ds}$. The complete model consists of the intrinsic model plus the parasitics. The apparent simplicity of the model is a result of hiding information in the characteristics of the nonlinear components. The resulted network model has been checked by simulation and analysis. It is shown that the network model is suitable for simulation: It is defined for any value of the voltages; the functions involved are continuous and satisfy Lipschitz conditions with no jumps at region boundaries; Derivatives have been computed symbolically and are available for use by the Newton-Raphson method. The model"s functions can be measured from the terminals. It is also shown that small channel effects can be included in the model. Higher frequency effects can be modeled by using a network consisting of several sections of the basic lumped model. Future plans include a detailed comparison of the network model with models such as SPICE level 3 and a comparison of the multi- section higher frequency model with experiments.

Development of CMOS-compatible electrostatic supercapacitors

This work focuses on development of electrostatic supercapacitors (ESCs) using process routes compatible with complementary metal–oxide–semiconductor (CMOS) fabrication. Wafer-scale anodised aluminium oxide (AAO) processing techniques have been developed to produce high-surface area templates. Statistically optimised atomic layer deposition (ALD) processes have been developed to conformally coat the templates and generate metalinsulator-metal capacitor structures. Detailed electrical characterisation and analysis for a range of devices, revealed ESC’s with high capacitance densities of ~12 μF cm-2 and equivalent energy densities of 0.28 Wh/kg . Finally the suitability of ESC’s toward next generation energy storage applications is discussed.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Atomic layer deposition of copper for CMOS interconnects

This work concerns the atomic layer deposition (ALD) of copper. ALD is a technique that allows conformal coating of difficult topographies such as narrow trenches and holes or even shadowed regions. However, the deposition of pure metals has so far been less successful than the deposition of oxides except for a few exceptions. Challenges include difficulties associated with the reduction of the metal centre of the precursor at reasonable temperatures and the tendency of metals to agglomerate during the growth process. Cu is a metal of special technical interest as it is widely used for interconnects on CMOS devices. These interconnects are usually fabricated by electroplating, which requires the deposition of thin Cu seed layers onto the trenches and vias. Here, ALD is regarded as potential candidate for replacing the current PVD technique, which is expected to reach its limitations as the critical dimensions continue to shrink. This work is separated into two parts. In the first part, a laboratory-scale ALD reactor was constructed and used for the thermal ALD of Cu. In the second part, the potentials of the application of Cu ALD on industry scale fabrication were examined in a joint project with Applied Materials and Intel. Within this project precursors developed by industrial partners were evaluated on a 300 mm Applied Materials metal-ALD chamber modified with a direct RF-plasma source. A feature that makes ALD a popular technique among researchers is the possibility to produce high- level thin film coatings for micro-electronics and nano-technology with relatively simple laboratory- scale reactors. The advanced materials and surfaces group (AMSG) at Tyndall National Institute operates a range of home-built ALD reactors. In order to carry out Cu ALD experiments, modifications to the normal reactor design had to be made. For example a carrier gas mechanism was necessary to facilitate the transport of the low-volatile Cu precursors. Precursors evaluated included the readily available Cu(II)-diketonates Cu-bis(acetylacetonate), Cu-bis(2,2,6,6-tetramethyl-hepta-3,5-dionate) and Cu-bis(1,1,1,5,5,5-hexafluoacetylacetonate) as well as the Cu-ketoiminate Cu-bis(4N-ethylamino- pent-3-en-2-onate), which is also known under the trade name AbaCus (Air Liquide), and the Cu(I)- silylamide 1,3-diisopropyl-imidazolin-2-ylidene Cu(I) hexamethyldisilazide ([NHC]Cu(hmds)), which was developed at Carleton University Ottawa. Forming gas (10 % H2 in Ar) was used as reducing agent except in early experiments where formalin was used. With all precursors an extreme surface selectivity of the deposition process was observed and significant growth was only achieved on platinum-group metals. Improvements in the Cu deposition process were obtained with [NHC]Cu(hmds) compared with the Cu(II) complexes. A possible reason is the reduced oxidation state of the metal centre. Continuous Cu films were obtained on Pd and indications for saturated growth with a rate of about 0.4 Å/cycle were found for deposition at 220 °C. Deposits obtained on Ru consisted of separated islands. Although no continuous films could be obtained in this work the relatively high density of Cu islands obtained was a clear improvement as compared to the deposits grown with Cu(II) complexes. When ultra-thin Pd films were used as substrates, island growth was also observed. A likely reason for this extreme difference to the Cu films obtained on thicker Pd films is the lack of stress compensation within the thin films. The most likely source of stress compensation in the thicker Pd films is the formation of a graded interlayer between Pd and Cu by inter-diffusion. To obtain continuous Cu films on more materials, reduction of the growth temperature was required. This was achieved in the plasma assisted ALD experiments discussed in the second part of this work. The precursors evaluated included the AbaCus compound and CTA-1, an aliphatic Cu-bis(aminoalkoxide), which was supplied by Adeka Corp.. Depositions could be carried out at very low temperatures (60 °C Abacus, 30 °C CTA-1). Metallic Cu could be obtained on all substrate materials investigated, but the shape of the deposits varied significantly between the substrate materials. On most materials (Si, TaN, Al2O3, CDO) Cu grew in isolated nearly spherical islands even at temperatures as low as 30 °C. It was observed that the reason for the island formation is the coalescence of the initial islands to larger, spherical islands instead of forming a continuous film. On the other hand, the formation of nearly two-dimensional islands was observed on Ru. These islands grew together forming a conductive film after a reasonably small number of cycles. The resulting Cu films were of excellent crystal quality and had good electrical properties; e.g. a resistivity of 2.39 µΩ cm was measured for a 47 nm thick film. Moreover, conformal coating of narrow trenches (1 µm deep 100/1 aspect ratio) was demonstrated showing the feasibility of the ALD process.

Piezopotential gated nanowire--nanotube hybrid field-effect transistor.

We report the first piezoelectric potential gated hybrid field-effect transistors based on nanotubes and nanowires. The device consists of single-walled carbon nanotubes (SWNTs) on the bottom and crossed ZnO piezoelectric fine wire (PFW) on the top with an insulating layer between. Here, SWNTs serve as a carrier transport channel, and a single-crystal ZnO PFW acts as the power-free, contact-free gate or even an energy-harvesting component later on. The piezopotential created by an external force in the ZnO PFW is demonstrated to control the charge transport in the SWNT channel located underneath. The magnitude of the piezopotential in the PFW at a tensile strain of 0.05% is measured to be 0.4-0.6 V. The device is a unique coupling between the piezoelectric property of the ZnO PFW and the semiconductor performance of the SWNT with a full utilization of its mobility. The newly demonstrated device has potential applications as a strain sensor, force/pressure monitor, security trigger, and analog-signal touch screen.

Accurate substrate modelling of RF CMOS

The losses within the substrate of an RF IC can have significant effect on performance in a mixed signal application. in order to model substrate coupling accurately, it is represented by an RC network to account for both resistive and dielectric losses at high frequency (> 1 GHz). A small-signal equivalent circuit model of an RF IC inclusive of substrate parasitic effect is analysed in terms of its y-parameters and an extraction procedure for substrate parameters has been developed. By coupling the extracted substrate parameters along with extrinsic resistances associated with gate, source and drain, a standard BSIM3 model has been extended for RF applications. The new model exhibits a significant improvement in prediction of output reflection coefficient S-22 in the frequency range from 1 to 10 GHz in device mode of operation and for a low noise amplifier (LNA) at 2.4 GHz. Copyright (C) 2006 John Wiley & Sons, Ltd.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Extrinsic parameter extraction and RF modelling of CMOS

An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation. (C) 2003 Elsevier Ltd. All rights reserved.