A single microphone capillary-based system for measuring the complex input impedance of musical wind instruments

Capillary-based systems for measuring the input impedance of musical wind instruments were first developed in the mid-20th century and remain in widespread use today. In this paper, the basic principles and assumptions underpinning the design of such systems are examined. Inexpensive modifications to a capillary-based impedance measurement set-up made possible due to advances in computing and data acquisition technology are discussed. The modified set-up is able to measure both impedance magnitude and impedance phase even though it only contains one microphone. In addition, a method of calibration is described that results in a significant improvement in accuracy when measuring high impedance objects on the modified capillary-based system. The method involves carrying out calibration measurements on two different objects whose impedances are well-known theoretically. The benefits of performing two calibration measurements (as opposed to the one calibration measurement that has been traditionally used) are demonstrated experimentally through input impedance measurements on two test objects and a Boosey and Hawkes oboe. © S. Hirzel Verlag · EAA.

OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION.

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimized in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.

UTILISATION OF BIT LEVEL SYSTOLIC ARRAYS IN WORD LEVEL SYSTEMS.

Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.

BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.