Project of a bandgap voltage reference and a temperature sensor for "energy harvest" systems

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e Computadores

A radial basis function network (RBFN) for function approximation

A radial basis function network (RBFN) circuit for function approximation is presented. Simulation and experimental results show that the network has good approximation capabilities. The RBFN was a squared hyperbolic secant with three adjustable parameters amplitude, width and center. To test the network a sinusoidal and sine function,vas approximated.

Design and development of distributed feedback transistor lasers

The transistor laser is a unique three-port device that operates simultaneously as a transistor and a laser. With quantum wells incorporated in the base regions of heterojunction bipolar transistors, the transistor laser possesses advantageous characteristics of fast base spontaneous carrier lifetime, high differential optical gain, and electrical-optical characteristics for direct “read-out” of its optical properties. These devices have demonstrated many useful features such as high-speed optical transmission without the limitations of resonance, non-linear mixing, frequency multiplication, negative resistance, and photon-assisted switching. To date, all of these devices operate as multi-mode lasers without any type of wavelength selection or stabilizing mechanisms. Stable single-mode distributed feedback diode laser sources are important in many applications including spectroscopy, as pump sources for amplifiers and solid-state lasers, for use in coherent communication systems, and now as TLs potentially for integrated optoelectronics. The subject of this work is to expand the future applications of the transistor laser by demonstrating the theoretical background, process development and device design necessary to achieve singlelongitudinal- mode operation in a three-port transistor laser. A third-order distributed feedback surface grating is fabricated in the top emitter AlGaAs confining layers using soft photocurable nanoimprint lithography. The device produces continuous wave laser operation with a peak wavelength of 959.75 nm and threshold current of 13 mA operating at -70 °C. For devices with cleaved ends a side-mode suppression ratio greater than 25 dB has been achieved.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Electrochemical single-molecule transistors with optimized gate coupling

Electrochemical gating at the single molecule level of viologen molecular bridges in ionic liquids is examined. Contrary to previous data recorded in aqueous electrolytes, a clear and sharp peak in the single molecule conductance versus electrochemical potential data is obtained in ionic liquids. These data are rationalized in terms of a two-step electrochemical model for charge transport across the redox bridge. In this model the gate coupling in the ionic liquid is found to be fully effective with a modeled gate coupling parameter, ξ, of unity. This compares to a much lower gate coupling parameter of 0.2 for the equivalent aqueous gating system. This study shows that ionic liquids are far more effective media for gating the conductance of single molecules than either solid-state three-terminal platforms created using nanolithography, or aqueous media.

Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short- channel devices down to 30 nm at different temperatures have been also used to validate the model.

A novel self consistent calculation approach for the capacitance-voltage characteristics of semiconductor quantum wire transistors based on a split-gate configuration

Purpose - The purpose of this paper is to develop an efficient numerical algorithm for the self-consistent solution of Schrodinger and Poisson equations in one-dimensional systems. The goal is to compute the charge-control and capacitance-voltage characteristics of quantum wire transistors. Design/methodology/approach - The paper presents a numerical formulation employing a non-uniform finite difference discretization scheme, in which the wavefunctions and electronic energy levels are obtained by solving the Schrodinger equation through the split-operator method while a relaxation method in the FTCS scheme ("Forward Time Centered Space") is used to solve the two-dimensional Poisson equation. Findings - The numerical model is validated by taking previously published results as a benchmark and then applying them to yield the charge-control characteristics and the capacitance-voltage relationship for a split-gate quantum wire device. Originality/value - The paper helps to fulfill the need for C-V models of quantum wire device. To do so, the authors implemented a straightforward calculation method for the two-dimensional electronic carrier density n(x,y). The formulation reduces the computational procedure to a much simpler problem, similar to the one-dimensional quantization case, significantly diminishing running time.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Study of high-quality ALD gate dielectrics in radiation sensitive oxide field effect transistors

Radiation dosimetry is crucial in many fields, where the exposure of ionizing radiation must be precisely controlled to avoid health and environmental safety issues. Radiotherapy and radioprotection are two examples in which fast and reliable detectors are needed. Compact and large area wearable detectors are being developed to address real-life radiation dosimetry applications, their ideal properties include flexibility, lightness, and low-cost. This thesis contributed to the development of Radiation sensitive OXide Field Effect Transistors (ROXFETs), which are detectors able to provide fast and real-time radiation read out. ROXFETs are based on thin film transistors fabricated with high-mobility amorphous oxide semiconductor, making them compatible with large area, flexible, and low cost production over plastic substrates. The gate dielectric material has high dielectric constant and high atomic number, which results in high performances and high radiation sensitivity, respectively. The aim of this work was to establish a stable and reliable fabrication process for ROXFETs made with atomic layer deposited gate dielectric. A study on the effect of gate dielectric materials was performed, focusing the attention on the properties of the dielectric-semiconductor interface. Single and multi layer dielectric structures were compared during this work. Furthermore, the effect of annealing temperature was studied. The device performances were tested to understand the underlying physical processes. In this way, it was possible to determine a reliable fabrication procedure and an optimal structure for ROXFETs. An outstanding sensitivity of (65±3)V/Gy was measured in detectors with a bi-layer Ta₂O₅-Al₂O₃ gate dielectric with low temperature annealing performed at 180°C.

Bilayer graphene dual-gate nanodevice: An ab initio simulation

We study the electronic transport properties of a dual-gated bilayer graphene nanodevice via first-principles calculations. We investigate the electric current as a function of gate length and temperature. Under the action of an external electrical field we show that even for gate lengths up 100 angstrom, a nonzero current is exhibited. The results can be explained by the presence of a tunneling regime due the remanescent states in the gap. We also discuss the conditions to reach the charge neutrality point in a system free of defects and extrinsic carrier doping.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-a round (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the H D is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any Studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. (C) 2008 Elsevier Ltd. All rights reserved.

High-performance flexible hybrid field-effect transistors based on cellulose fiber paper

IEEE Electron Device Letters, VOL. 29, NO. 9,