Electro-optical properties of liquid crystal copolymers and their relationship to structural order

A range of side chain liquid crystal copolymers have been prepared using mesogenic and non-mesogenic units. It is found that high levels of the non-mesogenic moieties may be introduced without completely disrupting the organization of the liquid crystal phase. Incorporation of this comonomer causes a marked reduction in the glass transition temperature (Tg), presumably as a result of enhanced backbone mobility and a corresponding lowering of the nematic transition temperature, thereby restricting the temperature range for stability of the liquid crystal phase. The effect of the interactions between the various components of these side-chain polymers on their electro-optic responses is described. Infrared (i.r.) dichroism measurements have been made to determine the order parameters of the liquid crystalline side-chain polymers. By identifying a certain band (CN stretching) in the i.r. absorption spectrum, the order parameter of the mesogenic groups can be obtained. The temperature and composition dependence of the observed order parameter are related to the liquid crystal phase transitions and to the electro-optic response. It is found that the introduction of the non-mesogenic units into the polymer chain lowers the threshold voltage of the electro-optic response over and above that due to the reduction in the order parameter. The dynamic electro-optic responses are dominated by the temperature-dependent viscosity and evidence is presented for relaxation processes involving the polymer backbone which are on a time scale greater than that for the mesogenic side-chain units.

The effect of the molecular weight on the electro-optic properties of methacrylate-based side-chain liquid crystal polymers

A series of methacrylate-based side-chain liquid crystal polymers has been prepared with a range of molecular weights. For the high molecular weight polymers a smectic phase is observed with a very narrow nematic range; however, for low molecular weight polymers only the nematic phase is observed. A marked reduction in the glass transition temperature, TSN and TNI is observed with a reduction in the molecular weight. The orientational order parameters for these polymers in the liquid crystal phase have been determined using infra-red dichroism. It is found that the higher the molecular weight of the polymer, the greater is the threshold voltage of the electro-optic response and the lower the order parameter. The increase in the threshold voltage with increasing molecular weight may be related to the intrinsic curvature elasticity and hence to the coupling between the mesogenic units and the polymer backbone.

Electrical properties of polymer/metal interface in polymer light-emitting devices: electron injection barrier suppression

The electrical characterization of a high efficient multilayer polymer light emitting diode using poly[(2-methoxy-5-hexyloxy)-p-phenylenevinylene] as the emissive layer and an anionic fluorinated surfactant as the electron transport layer was performed. For the sake of comparison, a conventional single layer device was fabricated. The density current vs. voltage measurements revealed that the conventional device has a higher threshold voltage and lower current compared to the surfactant modified device. The effective barrier height for electron injection was suppressed. The influence of the interfaces and bulk contributions to the dc and high frequencies conductivities of the devices was also discussed. (c) 2006 Springer Science + Business Media, Inc.

Transporte e características de onda de densidade de carga na ludwigita nomometálica Fe3O2BO3

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Transporte eletrônico de nanofita de grafeno sob a influência de constrições e oxidação

Neste trabalho, investigamos os efeitos da funcionalização de grupos oxidativos sobre a estrutura de nanofitas de grafeno zigue-zague e também os efeitos de constrições, onde estes efeitos foram analisados por meio de transporte eletrônico via campo externo longitudinal. Nossos cálculos foram parametrizados pelo modelo semi-empírico de Huckel estendido-ETH, adotando-se o método das funções de Green de não equilíbrio- NEGF. As correntes foram calculadas via equação de Landauer que usa a função de transmissão da região espalhadora ao fluxo de elétrons com energia (E) vinda do eletrodo esquerdo. Por meio dessa abordagem, foi possível analisarmos o comportamento dos portadores de carga em cada um os dispositivos propostos, bem como, a natureza de tal comportamento. Verificaram-se nas curvas I(V) dois regimes de transporte: Ôhmico e NDR, verificando máximos de corrente e, também a tensão de limiar (VTh1

Performance of electronic devices submitted to X-rays and high energy proton beams

In this work we have studied the radiation effects on MOSFET electronic devices. The integrated circuits were exposed to 10 key X-ray radiation and 2.6 MeV energy proton beam. We have irradiated MOSFET devices with two different geometries: rectangular-gate transistor and circular-gate transistor. We have observed the cumulative dose provokes shifts on the threshold voltage and increases or decreases the transistor's off-state and leakage current. The position of the trapped charges in modern CMOS technology devices depends on radiation type, dose rate, total dose, applied bias and is a function of device geometry. We concluded the circular-gate transistor is more tolerant to radiation than the rectangular-gate transistor. (C) 2011 Elsevier B.V. All rights reserved.

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. (C) 2011 Elsevier Ltd. All rights reserved.

Behavior of triple-gate Bulk FinFETs with and without DTMOS operation

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance. Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristic; and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications. (C) 2011 Elsevier Ltd. All rights reserved.

The zero temperature coefficient in junctionless nanowire transistors

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows that ZTC may occur in JNTs depending mainly on the series resistance of the devices and its dependence on the temperature. Experimental results of drain current, threshold voltage, and series resistance are presented for both long and short channel n and p-type devices. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4744965]

UV-Ozone Generation from Modified High Intensity Discharge Mercury Vapor Lamps for Treatment of Indium Tin Oxide Films

In a homemade UV-Ozone generator, different ignition tubes extracted from HID mercury vapor lamps were investigated, namely: 80, 125, 250 and 400 watts. The performance of the generator in function of the type of the ignition lamp was monitored by the measurements of the ozone concentration and the temperature increment. The results have shown that the 400 W set up presented the highest ozone production, which was used in the treatment of indium tin oxide (ITO) films. Polymer light emitting diodes were assembled using ITO films, treated for 10, 20 and 30 min, as an anode. The overall results indicate improvement of the threshold voltage (reduction) and electroluminescence of these devices.

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

Ion implantation of organic thin films and electronic devices

Organic semiconductors have great promise in the field of electronics due to their low cost in term of fabrication on large areas and their versatility to new devices, for these reasons they are becoming a great chance in the actual technologic scenery. Some of the most important open issues related to these materials are the effects of surfaces and interfaces between semiconductor and metals, the changes caused by different deposition methods and temperature, the difficulty related to the charge transport modeling and finally a fast aging with time, bias, air and light, that can change the properties very easily. In order to find out some important features of organic semiconductors I fabricated Organic Field Effect Transistors (OFETs), using them as characterization tools. The focus of my research is to investigate the effects of ion implantation on organic semiconductors and on OFETs. Ion implantation is a technique widely used on inorganic semiconductors to modify their electrical properties through the controlled introduction of foreign atomic species in the semiconductor matrix. I pointed my attention on three major novel and interesting effects, that I observed for the first time following ion implantation of OFETs: 1) modification of the electrical conductivity; 2) introduction of stable charged species, electrically active with organic thin films; 3) stabilization of transport parameters (mobility and threshold voltage). I examined 3 different semiconductors: Pentacene, a small molecule constituted by 5 aromatic rings, Pentacene-TIPS, a more complex by-product of the first one, and finally an organic material called Pedot PSS, that belongs to the branch of the conductive polymers. My research started with the analysis of ion implantation of Pentacene films and Pentacene OFETs. Then, I studied totally inkjet printed OFETs made of Pentacene-TIPS or PEDOT-PSS, and the research will continue with the ion implantation on these promising organic devices.

Analysis of charge-transport properties in GST materials for next generation phase-change memory devices

The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. To resolve this issue the industry is improving existing technologies such as Flash and exploring new ones. Among those new technologies is the Phase Change Memory (PCM), which overcomes some of the shortcomings of the Flash such as durability and scalability. This alternative non-volatile memory technology, which uses resistance contrast in phase-change materials, offers more density relative to DRAM, and can help to increase main memory capacity of future systems while remaining within the cost and power constraints. Chalcogenide materials can suitably be exploited for manufacturing phase-change memory devices. Charge transport in amorphous chalcogenide-GST used for memory devices is modeled using two contributions: hopping of trapped electrons and motion of band electrons in extended states. Crystalline GST exhibits an almost Ohmic I(V) curve. In contrast amorphous GST shows a high resistance at low biases while, above a threshold voltage, a transition takes place from a highly resistive to a conductive state, characterized by a negative differential-resistance behavior. A clear and complete understanding of the threshold behavior of the amorphous phase is fundamental for exploiting such materials in the fabrication of innovative nonvolatile memories. The type of feedback that produces the snapback phenomenon is described as a filamentation in energy that is controlled by electron–electron interactions between trapped electrons and band electrons. The model thus derived is implemented within a state-of-the-art simulator. An analytical version of the model is also derived and is useful for discussing the snapback behavior and the scaling properties of the device.

Parallel Architectures for Many-Core Systems-On-Chip in Deep Sub-Micron Technology

Despite the several issues faced in the past, the evolutionary trend of silicon has kept its constant pace. Today an ever increasing number of cores is integrated onto the same die. Unfortunately, the extraordinary performance achievable by the many-core paradigm is limited by several factors. Memory bandwidth limitation, combined with inefficient synchronization mechanisms, can severely overcome the potential computation capabilities. Moreover, the huge HW/SW design space requires accurate and flexible tools to perform architectural explorations and validation of design choices. In this thesis we focus on the aforementioned aspects: a flexible and accurate Virtual Platform has been developed, targeting a reference many-core architecture. Such tool has been used to perform architectural explorations, focusing on instruction caching architecture and hybrid HW/SW synchronization mechanism. Beside architectural implications, another issue of embedded systems is considered: energy efficiency. Near Threshold Computing is a key research area in the Ultra-Low-Power domain, as it promises a tenfold improvement in energy efficiency compared to super-threshold operation and it mitigates thermal bottlenecks. The physical implications of modern deep sub-micron technology are severely limiting performance and reliability of modern designs. Reliability becomes a major obstacle when operating in NTC, especially memory operation becomes unreliable and can compromise system correctness. In the present work a novel hybrid memory architecture is devised to overcome reliability issues and at the same time improve energy efficiency by means of aggressive voltage scaling when allowed by workload requirements. Variability is another great drawback of near-threshold operation. The greatly increased sensitivity to threshold voltage variations in today a major concern for electronic devices. We introduce a variation-tolerant extension of the baseline many-core architecture. By means of micro-architectural knobs and a lightweight runtime control unit, the baseline architecture becomes dynamically tolerant to variations.

Optimization of purification procedures in organic semiconductor synthesis for improving the performances of organic field-effect transistors

The aim of the research activity focused on the investigation of the correlation between the degree of purity in terms of chemical dopants in organic small molecule semiconductors and their electrical and optoelectronic performances once introduced as active material in devices. The first step of the work was addressed to the study of the electrical performances variation of two commercial organic semiconductors after being processed by means of thermal sublimation process. In particular, the p-type 2,2′′′-Dihexyl-2,2′:5′,2′′:5′′,2′′′-quaterthiophene (DH4T) semiconductor and the n-type 2,2′′′- Perfluoro-Dihexyl-2,2′:5′,2′′:5′′,2′′′-quaterthiophene (DFH4T) semiconductor underwent several sublimation cycles, with consequent improvement of the electrical performances in terms of charge mobility and threshold voltage, highlighting the benefits brought by this treatment to the electric properties of the discussed semiconductors in OFET devices by the removal of residual impurities. The second step consisted in the provision of a metal-free synthesis of DH4T, which was successfully prepared without organometallic reagents or catalysts in collaboration with Dr. Manuela Melucci from ISOF-CNR Institute in Bologna. Indeed the experimental work demonstrated that those compounds are responsible for the electrical degradation by intentionally doping the semiconductor obtained by metal-free method by Tetrakis(triphenylphosphine)palladium(0) (Pd(PPh3)4) and Tributyltin chloride (Bu3SnCl), as well as with an organic impurity, like 5-hexyl-2,2':5',2''-terthiophene (HexT3) at, in different concentrations (1, 5 and 10% w/w). After completing the entire evaluation process loop, from fabricating OFET devices by vacuum sublimation with implemented intentionally-doped batches to the final electrical characterization in inherent-atmosphere conditions, commercial DH4T, metal-free DH4T and the intentionally-doped DH4T were systematically compared. Indeed, the fabrication of OFET based on doped DH4T clearly pointed out that the vacuum sublimation is still an inherent and efficient purification method for crude semiconductors, but also a reliable way to fabricate high performing devices.