Enabling Leg-Based Guidance on Top of Waypoint-Based Autopilots for UAS

This paper presents a methodology to extend the guidance functionalities of Commercial Off-The-Shelf autopilots currently available for Unmanned Aircraft Systems (UAS). Providing that most autopilots only support elemental waypoint-based guidance, this technique allows the aircraft to follow leg-based flight plans without needing to modify the internal control algorithms of the autopilot. It is discussed how to provide Direct to Fix, Track to Fix and Hold to Fix path terminators (along with Fly-Over and Fly-By waypoints) to basic autopilots able to natively execute only a limited set of legs. Preliminary results show the feasibility of the proposal with flight simulations that used a flexible and reconfigurable UAS architecture specifically designed to avoid dependencies with a single or particular autopilot solution.

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio.

Optimal day-ahead scheduling of integrated urban energy systems

An optimal day-ahead scheduling method (ODSM) for the integrated urban energy system (IUES) is introduced, which considers the reconfigurable capability of an electric distribution network. The hourly topology of a distribution network, a natural gas network, the energy centers including the combined heat and power (CHP) units, different energy conversion devices and demand responsive loads (DRLs), are optimized to minimize the day-ahead operation cost of the IUES. The hourly reconfigurable capability of the electric distribution network utilizing remotely controlled switches (RCSs) is explored and discussed. The operational constraints from the unbalanced three-phase electric distribution network, the natural gas network, and the energy centers are considered. The interactions between the electric distribution network and the natural gas network take place through conversion of energy among different energy vectors in the energy centers. An energy conversion analysis model for the energy center was developed based on the energy hub model. A hybrid optimization method based on genetic algorithm (GA) and a nonlinear interior point method (IPM) is utilized to solve the ODSM model. Numerical studies demonstrate that the proposed ODSM is able to provide the IUES with an effective and economical day-ahead scheduling scheme and reduce the operational cost of the IUES.

FPGA-based architecture for hyperspectral endmember extraction

Hyperspectral instruments have been incorporated in satellite missions, providing data of high spectral resolution of the Earth. This data can be used in remote sensing applications, such as, target detection, hazard prevention, and monitoring oil spills, among others. In most of these applications, one of the requirements of paramount importance is the ability to give real-time or near real-time response. Recently, onboard processing systems have emerged, in order to overcome the huge amount of data to transfer from the satellite to the ground station, and thus, avoiding delays between hyperspectral image acquisition and its interpretation. For this purpose, compact reconfigurable hardware modules, such as field programmable gate arrays (FPGAs) are widely used. This paper proposes a parallel FPGA-based architecture for endmember’s signature extraction. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data sets collected by the NASA’s Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems, opening new perspectives for onboard hyperspectral image processing.

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

Operating infrastructure for an FPGA and ARM system

Advances in FPGA technology and higher processing capabilities requirements have pushed to the emerge of All Programmable Systems-on-Chip, which incorporate a hard designed processing system and a programmable logic that enable the development of specialized computer systems for a wide range of practical applications, including data and signal processing, high performance computing, embedded systems, among many others. To give place to an infrastructure that is capable of using the benefits of such a reconfigurable system, the main goal of the thesis is to implement an infrastructure composed of hardware, software and network resources, that incorporates the necessary services for the operation, management and interface of peripherals, that coompose the basic building blocks for the execution of applications. The project will be developed using a chip from the Zynq-7000 All Programmable Systems-on-Chip family.

Reuse and integration of specification logics: the hybridisation perspective

Hybridisation is a systematic process along which the characteristic features of hybrid logic, both at the syntactic and the semantic levels, are developed on top of an arbitrary logic framed as an institution. It also captures the construction of first-order encodings of such hybridised institutions into theories in first-order logic. The method was originally developed to build suitable logics for the specification of reconfigurable software systems on top of whatever logic is used to describe local requirements of each system’s configuration. Hybridisation has, however, a broader scope, providing a fresh example of yet another development in combining and reusing logics driven by a problem from Computer Science. This paper offers an overview of this method, proposes some new extensions, namely the introduction of full quantification leading to the specification of dynamic modalities, and exemplifies its potential through a didactical application. It is discussed how hybridisation can be successfully used in a formal specification course in which students progress from equational to hybrid specifications in a uniform setting, integrating paradigms, combining data and behaviour, and dealing appropriately with systems evolution and reconfiguration.

A ansiedade infantil : vulnerabilidades da criança e influência dos pais

Tese de Doutoramento em Psicologia na área de especialidade Psicologia Clínica

A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.

Curated Commons: The Maryland Model

The curated commons is a model in which a flexible library building shell and its infrastructure can respond to the specific time-sensitive needs of differing clients. It applies to faculty research, in particular small science activities (as opposed to big science activities that have major support which includes proprietary laboratories and facilities). It provides for sustained transformation of library facilities as well as its utilitarian and cyber-infrastructures to become a flexible reconfigurable space with cutting edge technology and sustained funding streams.

A participação das forças armadas na segurança pública de Cabo Verde: que colaboração?

Tendo em conta o nível de desenvolvimento que Cabo Verde tem vindo a conhecer, o crescimento rápido da sua população, o aparecimento de novos factos criminais e ainda o facto de possuir um enorme Zona Económica Exclusiva, associado ao facto de ser um país de fracos recursos económicos, é motivo para que se optimizem os recursos, encontrando respostas legalmente adequadas, eficazes e eficientes ao fenómeno do crime e da insegurança, projectados pelas novas ameaças. Com a revisão Constitucional de 1999, as Forças Armadas (FA) ganharam competência no âmbito de segurança interna, para colaborem com as Forças e Serviços de Segurança (FSS) e sob a responsabilidade destas. Este estudo debruça sobre “A Participação das Forças Armadas na Segurança Pública em Cabo Verde”, no intuito de analisar e perceber que tipo de colaboração prevê a Constituição, perceber à que nível pode ocorrer a actuação das FA na segurança e ordem pública e quais os limites dessa actuação. Para fazer o estudo recorreu-se à análise documental e fez-se uso do método de qualitativo, tendo como instrumento de recolha de informação a entrevista (semiestruturada), seguido de uma análise de conteúdo permitindo confrontar os resultados com as ideias existentes no enquadramento teórico. Conclui-se que as FA têm competências para actuar na segurança interna somente em colaboração com as FSS. Mas mostra-se que perante o quadro socioeconómico de Cabo Verde não se pode dispensar esta colaboração.

Fadiga em pacientes da Coorte Brasília de artrite reumatoide (AR) : estudo da prevalência e comparação entre diferentes instrumentos de avaliação

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Medicina, Programa de Pós-Graduação em Ciências Médicas, 2016.

Applicazione di un modello bi-obiettivo per la progettazione sostenibile di sistemi produttivi riconfigurabili

Negli ultimi anni la competitività nei mercati è notevolmente cresciuta, la complessità dei prodotti industriali è considerevolmente aumentata e quest’ultimi devono ora essere accuratamente ottimizzati sotto ogni aspetto. I prodotti, oltre ad avere dei cicli di vita più brevi, sono soggetti a un’alta personalizzazione e a una domanda variabile. Per rimanere competitive, le aziende manifatturiere devono possedere nuovi tipi di sistemi di produzione che siano convenienti e molto reattivi a tutti questi cambiamenti del mercato, quali i Sistemi di produzione riconfigurabili (Reconfigurable Manufacturing System - RMS). La particolarità di tali sistemi risiede nella capacità di cambiare rapidamente le loro strutture hardware e software, aspetto che li renda idonei a soddisfare la produzione moderna. Oltre agli aspetti produttivi, l’attenzione odierna è incentrata anche sulle tematiche ambientali legate al risparmio energetico durante i processi produttivi, alla riduzione delle quantità di CO2 emesse e alla sostenibilità ambientale. L’obiettivo di questa tesi è quello di proporre un modello di ottimizzazione multi-obiettivo che tenga conto sia della minimizzazione del tempo complessivo necessario alla movimentazione dei prodotti e alla riconfigurazione delle macchine, e sia della minimizzazione del consumo energetico. Tale modello è stato applicato ad un caso studio realistico che ha permesso di individuare un trade-off tecnico-ambientale individuando la frontiera di Pareto con punto di ottimo (134.6 min; 9346.3 kWh) che si discosta del 57% dal valore trovato ottimizzando la funzione tempo, e dello 0.76% dal valore ottenuto ottimizzando la funzione energia.

Innovative layout design and radiated harmonic analysis for advanced frequency-diverse array solutions

Wireless power transfer is becoming a crucial and demanding task in the IoT world. Despite the already known solutions exploiting a near-field powering approach, far-field WPT is definitely more challenging, and commercial applications are not available yet. This thesis proposes the recent frequency-diverse array technology as a potential candidate for realizing smart and reconfigurable far-field WPT solutions. In the first section of this work, an analysis on some FDA systems is performed, identifying the planar array with circular geometry as the most promising layout in terms of radiation properties. Then, a novel energy aware solution to handle the critical time variability of the FDA beam pattern is proposed. It consists on a time-control strategy through a triangular pulse, and it allows to achieve ad-hoc and real time WPT. Moreover, an essential frequency domain analysis of the radiating behaviour of a pulsed FDA system is presented. This study highlights the benefits of exploiting the intrinsic pulse harmonics for powering purposes, thus minimising the power loss. Later, the electromagnetic design of a radial FDA architecture is addressed. In this context, an exhaustive investigation on miniaturization techniques is carried out; the use of multiple shorting pins together with a meandered feeding network has been selected as a powerful solution to halve the original prototype dimension. Finally, accurate simulations of the designed radial FDA system are performed, and the obtained results are given.

Soluzioni per coperture wireless in ambiente indoor con l'ausilio di superfici intelligenti riconfigurabili

I sistemi di comunicazione 6G si prevede che soddisfino requisiti più stringenti rispetto alle reti 5G in termini di capacità di trasmissione, affidabilità, latenza, copertura, consumo energetico e densità di connessione. I miglioramenti che si possono ottenere agendo solo sugli end-points dell'ambiente wireless potrebbero non essere sufficienti per adempiere a tali obiettivi. Performance migliori potrebbero invece essere raggiunte liberandosi del postulato che fissa l'ambiente di propagazione come elemento incontrollabile. In questo panorama spicca una tecnologia recente che prende il nome di Reconfigurable Intelligent Surface (RIS) e che si pone l'obiettivo di rendere personalizzabile l'ambiente di propagazione wireless attraverso elaborazioni quasi passive di segnale. Una RIS è una superficie sottile ingegnerizzata al fine di possedere proprietà che le permettono di controllare dinamicamente le onde elettromagnetiche attraverso, ad esempio, la riflessione, rifrazione e focalizzazione del segnale. Questo può portare alla realizzazione del cosiddetto Smart Radio Environment (SRE), ovvero un ambiente di propagazione che non è visto come entità aleatoria incontrollabile, ma come parametro di design che svolge un ruolo fondamentale nel processo di ottimizzazione della rete. Nel presente elaborato, partendo da un modello macroscopico del comportamento di una RIS sviluppato dal gruppo di ricerca di propagazione e integrato all'interno di un simulatore di ray tracing, si effettua uno studio di coperture wireless con l'ausilio di RIS in semplici scenari indoor di riferimento.