Simultaneously multiply-configurable or superposed molecular logic systems composed of ICT (internal charge transfer) chromophores and fluorophores integrated with one- or two-ion receptors

Integrated "ICT chromophore-receptor" systems show ion-induced shifts in their electronic absorption spectra. The wavelength of observation can be used to reversibly configure the system to any of the four logic operations permissible with a single input (YES, NOT, PASS 1, PASS 0), under conditions of ion input and transmittance output. We demonstrate these with dyes integrated into Tsien's calcium receptor, 1-2. Applying multiple ion inputs to 1-2 also allows us to perform two- or three-input OR or NOR operations. The weak fluorescence output of 1 also shows YES or NOT logic depending on how it is configured by excitation and emission wavelengths. Integrated "receptor(1)-ICT chromophore-receptor(2)" systems 3-5 selectively target two ions into the receptor terminals. The ion-induced transmittance output of 3-5 can also be configured via wavelength to illustrate several logic types including, most importantly, XOR. The opposite effects of the two ions on the energy of the chromophore excited state is responsible for this behaviour. INHIBIT and REVERSE IMPLICATION are two of the other logic types seen here. Integration of XOR logic with a preceding OR operation can be arranged by using three ion inputs. The fluorescence output of these systems can be configured via wavelength to display INHIBIT or NOR logic under two-input conditions. The superposition or multiplicity of logic gate configurations is an unusual consequence of the ability to simultaneously observe multiple wavelengths.

Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.