"Plateau"-related summary statistics are uninformative for comparing working memory models.

Performance on visual working memory tasks decreases as more items need to be remembered. Over the past decade, a debate has unfolded between proponents of slot models and slotless models of this phenomenon (Ma, Husain, Bays (Nature Neuroscience 17, 347-356, 2014). Zhang and Luck (Nature 453, (7192), 233-235, 2008) and Anderson, Vogel, and Awh (Attention, Perception, Psychophys 74, (5), 891-910, 2011) noticed that as more items need to be remembered, "memory noise" seems to first increase and then reach a "stable plateau." They argued that three summary statistics characterizing this plateau are consistent with slot models, but not with slotless models. Here, we assess the validity of their methods. We generated synthetic data both from a leading slot model and from a recent slotless model and quantified model evidence using log Bayes factors. We found that the summary statistics provided at most 0.15 % of the expected model evidence in the raw data. In a model recovery analysis, a total of more than a million trials were required to achieve 99 % correct recovery when models were compared on the basis of summary statistics, whereas fewer than 1,000 trials were sufficient when raw data were used. Therefore, at realistic numbers of trials, plateau-related summary statistics are highly unreliable for model comparison. Applying the same analyses to subject data from Anderson et al. (Attention, Perception, Psychophys 74, (5), 891-910, 2011), we found that the evidence in the summary statistics was at most 0.12 % of the evidence in the raw data and far too weak to warrant any conclusions. The evidence in the raw data, in fact, strongly favored the slotless model. These findings call into question claims about working memory that are based on summary statistics.

Correlations strike back (again): The case of associative memory retrieval

It has long been recognised that statistical dependencies in neuronal activity need to be taken into account when decoding stimuli encoded in a neural population. Less studied, though equally pernicious, is the need to take account of dependencies between synaptic weights when decoding patterns previously encoded in an auto-associative memory. We show that activity-dependent learning generically produces such correlations, and failing to take them into account in the dynamics of memory retrieval leads to catastrophically poor recall. We derive optimal network dynamics for recall in the face of synaptic correlations caused by a range of synaptic plasticity rules. These dynamics involve well-studied circuit motifs, such as forms of feedback inhibition and experimentally observed dendritic nonlinearities. We therefore show how addressing the problem of synaptic correlations leads to a novel functional account of key biophysical features of the neural substrate.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

A nanowire magnetic memory cell based on a periodic magnetic superlattice

We analyse the operation of a semiconductor nanowire-based memory cell. Large changes in the nanowire conductance result when the magnetization of a periodic array of nanoscale magnetic gates, which comprise the other key component of the memory cell, is switched between distinct configurations by an external magnetic field. The resulting conductance change provides the basis for a robust memory effect, which can be implemented in a semiconductor structure compatible with conventional semiconductor integrated circuits.

Memory effect in a system of zincblende Mn-rich Mn(Ga)As nanoclusters embedded in GaAs

Zincblende Mn-rich Mn(Ga)As nanoclusters embedded in GaAs matrices are fabricated by in situ postgrowth annealing diluted magnetic semiconductor (Ga,Mn)As films with Mn concentration ranging from 2.6% to 8% at 650 degrees C. Magnetization measurements show that memory effect and slow magnetic relaxation, the typical characteristics of the spin-glass-like phase, occur below the blocking temperature of 45 K in samples with high Mn concentration, while for samples with low Mn concentration, ferromagnetic order remains up to 360 K. The behavior of low-temperature spin dynamics can be explained by the hierarchical model. (c) 2007 American Institute of Physics.

A time-varying controllable fault-tolerant field associative memory model and its simulation

A time-varying controllable fault-tolerant field associative memory model and the realization algorithms are proposed. On the one hand, this model simulates the time-dependent changeability character of the fault-tolerant field of human brain's associative memory. On the other hand, fault-tolerant fields of the memory samples of the model can be controlled, and we can design proper fault-tolerant fields for memory samples at different time according to the essentiality of memory samples. Moreover, the model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. And the fault-tolerant fields of the memory samples are full of the whole real space R-n. The simulation shows that the model has the above characters and the speed of associative memory about the model is faster.

The design algorithm of an associative memory neural network

A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.

Study on Mg memory effect in npn type AlGaN/GaN HBT structures grown by MOCVD

AlGaN/GaN npn heterojunction bipolar transistor structures were grown by low-pressure MOCVD. Secondary ion mass spectroscopy (SIMS) measurements were carried out to study the Mg memory effect and redistribution in the emitter-base junction. The results indicated that there is a Mg-rich film formed in the ongrowing layer after the Cp2Mg source is switched off. The Mg-rich film can be confined in the base section by switching off the Cp2Mg source for appropriate time before the end of base growth. Low temperature growth of the undoped GaN spacer suppresses the Mg redistribution from Mg rich film. The delay rate of the Mg profile in sample C with spacer growing in low temperature is about 56 nm/decade, which becomes sharper than 80 nm/decade of the samples A and B without low temperature spacer. (C) 2005 Elsevier Ltd. All rights reserved.

Photon-storage in optical memory cells based on a semiconductor quantum dot-quantum well hybrid structure

We report a new type of photonic memory cell based on a semiconductor quantum dot (QD)-quantum well (QW) hybrid structure, in which photo-generated excitons can be decomposed into separated electrons and holes, and stored in QW and QDs respectively. Storage and retrieval of photonic signals are verified by time-resolved photoluminescence experiments. A storage time in excess of 100ms has been obtained at a temperature of 10 K while the switching speed reaches the order of ten megahertz.

In-Situ Boron and Aluminum Doping and Their Memory Effects in 4H-SiC Homoepitaxial Layers Grown by Hot-Wall LPCVD

The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52x10(20) cm(-3) with Hall mobility of about 1 cm(2)/Vs and resistivity of 1.6 similar to 2.2x10(-2) Omega cm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Omega cm for resistivity, 5.3x10(18) cm(-3) for hole carrier concentration, and 7 cm(2)/VS for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Fully lithography independent fabrication of nanogap electrodes for lateral phase-change random access memory application

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