Vitellogenin in rare minnow (Gobiocypris rarus): identification and induction by waterborne diethylstilbestrol

Rare minnow (Gobiocypris rarus) is a tiny Chinese carp that has a short life cycle and is easily cultured in the laboratory. In this study, juvenile rare minnows were exposed to waterborne diethylstilbestrol (DES) at 0.05, 0.5 and 5 mug/l in laboratory aquaria. After exposure for 4, 8, 13 and 21 days, juvenile fish were collected and vitellogenin (Vtg) was measured in whole body homogenates. Native and SDS electrophoresis followed by Western blotting were performed for Vtg identification, and a non-competitive ELISA was developed. In the DES exposure groups (0.5 and 5 mug/l DES), Vtg appeared after 4 days, increased significantly after 8 days and reached a maximum on day 13. Further, a significant increase in the hepatosomatic index (HSI) was found in the 5 mug/l DES exposure group after 21 days. These results indicate that rare minnow provides a good model for assessing endocrine disruption by environmental estrogens. (C) 2004 Elsevier Inc. All rights reserved.

Induction of apoptosis in a carp leucocyte cell line infected with turbot (Scophthalmus maximus L.) rhabdovirus

A rhabdovirus was observed from the diseased turbot (Scophthalmus maximus L.) with lethal syndrome. In this study, a carp leucocyte (CLC) cell line was used to investigate the infection process and cell death mechanism occurring during the virus infection. Strong cytopathogenic effect (CPE) and the morphological changes, such as extreme chromatin condensation, nucleus fragmentation, and apoptotic body formation, were observed under fluorescence microscopy after DAPI staining in the infected CLC cells. Transmission electron microscopy analysis showed cell shrinkage, plasma membrane blebbing, cytoplasm vacuolization, chromatin condensation, nuclear breakdown and formation of discrete apoptotic bodies. The bullet-shaped nucleocapsids were measured and ranged in size from 110 to 150 nm in length and 40 to 60 nm in diameter. And therefore the virus is called Scophthalmus maximus rhabdovirus (SMRV). Agarose gel electrophoresis analysis of the DNA extracted from infected cells showed typical DNA ladder in the course of SMRV infection. Flow cytometry analysis of SMRV infected CLC cells detected apoptotic peak in the virus infected CLC cells. Virus titre analysis and electron microscopic observation revealed that the virus replication fastigium was earlier than that of the apoptosis occurrence. No apoptosis was observed in the CLC infected with UV-inactivated SMRV. All these supported that SMRV infected CLC cells undergo apoptosis and the virus replication is necessary for apoptosis induction of CLC cells. (C) 2004 Published by Elsevier B.V.

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Photonic switch and NOT logic gate based on the hybrid integration of a GaAsVCSEL and a GaAs MISS

The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators

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A logic for default reasoning

The need to make default assumptions is frequently encountered in reasoning about incompletely specified worlds. Inferences sanctioned by default are best viewed as beliefs which may well be modified or rejected by subsequent observations. It is this property which leads to the non-monotonicity of any logic of defaults. In this paper we propose a logic for default reasoning. We then specialize our treatment to a very large class of commonly occuring defaults. For this class we develop a complete proof theory and show how to interface it with a top down resolution theorem prover. Finally, we provide criteria under which the revision of derived beliefs must be effected.