In-Situ Boron and Aluminum Doping and Their Memory Effects in 4H-SiC Homoepitaxial Layers Grown by Hot-Wall LPCVD

The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52x10(20) cm(-3) with Hall mobility of about 1 cm(2)/Vs and resistivity of 1.6 similar to 2.2x10(-2) Omega cm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Omega cm for resistivity, 5.3x10(18) cm(-3) for hole carrier concentration, and 7 cm(2)/VS for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Fully lithography independent fabrication of nanogap electrodes for lateral phase-change random access memory application

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Dual-wavelength photochromic fulgides for parallel recording memory

Two photochromic fulgides, 2-{2-[4-(N,N-dimethylnilino)-5-methyl-4-oxazoly]}ethylidene-4-(1-methylethylidene) tetrahydrofuran-2,5-dione (A) and 3-(1,2-dimethyl-5-phenyl-3-pyrolloethylidene)-4-(1-methylethylidene)tetrahydrofuran-2,5-dione (B), doped in PMMA as candidates of dual-wavelength optical memory for parallel recording has been investigated. With 488 nm-laser and 650 nm-laser, both "cross" and "star" images are recorded on the fulgides-PMMA film and read out clearly, respectively. Crosstalk between two fulgides in PMMA matrix and nondestructive readout has also been explored. The results show that no significant cross-talk is detected between them, and nondestructive readout is up to 201 times. (C) 2005 Elsevier B.V. All rights reserved.

Analysis of orthogonal memory patterns

It is well known that the storage capacity may be large if all memory patterns are orthogonal to each other. In this paper, a clear description is given about the relation between the dimension N and the maximal number of orthogonal vectors with components +/-1, and also the conception of attractive index is proposed to estimate the basin of attraction. Theoretic analysis and computer simulation show that each memory pattern's basin of attraction contains at least one Hamming ball when the storage capacity is less than 0.33N which is better than usual 0.15 N.

Realization of write-once-read-many-times memory devices based on poly(N-vinylcarbazole) by thermally annealing

A nonvolatile write-once-read-many-time (WORM-time) memory device based on poly(N-vinylcarbazole) (PVK) films was realized by thermally annealing. The device can be fabricated using a simple spin coat method. It was found that the control of PVK film surface morphology by thermally annealing plays an important role in achieving the WORM memory properties. The memory device showed an ON/OFF current ratio as high as 10(4) and the retention time was over 2000 s without degradation.

The morphology control of pentacene for write-once-read-many-times memory devices

We realized write-once-read-many-times (WORM) memory devices based on pentacene and demonstrated that the morphology control of the vacuum deposited pentacene thin film is greatly important for achieving the unique nonvolatile memory properties. The resulted memory devices show a high ON/OFF current ratio (10(4)), long retention time (over 12 h), and good storage stability (over 240 h). The reduction of the barrier height caused by a large interface dipole and the damage of the interface dipole under a critical bias voltage have been used to explain the transition processes.

Origin of negative differential resistance and memory characteristics in organic devices based on tris(8-hydroxyquinoline) aluminum

Negative differential resistance (NDR) and memory phenomenon have been realized in current-voltage (I-V) characteristics of indium tin oxide/tris(8-hydroxyquinoline) aluminum/aluminum devices. The I-V curves have been divided into three operational regions that are associated with different working regimes of the devices: (i) bistable region, (ii) NDR region, and (iii) monotonic region. The bistable region disappeared after a couple of voltage sweeps from zero to a positive voltage. The bistable nature can be reinstated by applying a suitable negative voltage.

Organic Thin-Film Transistor Memory With Nanoparticle Floating Gate

Organic thin-film transistor memory devices were realized by inserting a layer of nanoparticles (such as Ag or CaF2) between two Nylon 6 gate dielectrics as the floating gate. The transistor memories were fabricated on glass substrates by full thermal deposition. The transistors exhibit significant hysteresis behavior in current-voltage characteristics, due to the separated Ag or CaF2 nanoparticle islands that act as charge trap centers. The mechanism of the transistor memory operation was discussed.