Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SCI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. (C) 2009 Elsevier Ltd. All rights reserved.

A low-temperature insulating phase at v=1.5 for 2D holes in high-mobility SiSi1-xGex heterostructures with Landau level degeneracy

Magneto-transport measurements of the 2D hole system (2DHS) in p-type Si-Si1-xGex heterostructures identify the integer quantum Hall effect (IQHE) at dominantly odd-integer filling factors v and two low-temperature insulating phases (IPs) at v = 1.5 and v less than or similar to 0.5, with re-entrance to the quantum Hall effect at v = 1. The temperature dependence, current-voltage characteristics, and tilted field and illumination responses of the IP at v = 1.5 indicate that the important physics is associated with an energy degeneracy of adjacent Landau levels of opposite spin, which provides a basis for consideration of an intrinsic, many-body origin.

Properties and function of KCNQ1 K+ channels isolated from the rectal gland of Squalus acanthias

KCNQ1 (K(V)LQT1) K+ channels play an important role during electrolyte secretion in airways and colon. KCNQ1 was cloned recently from NaCl-secreting shark rectal glands. Here we study. the properties and regulation of the cloned sK(V)LQT1 expressed in Xenopus oocytes and Chinese hamster ovary (CHO) cells and compare the results with those obtained from in vitro perfused rectal gland tubules (RGT). The expression of sKCNQ1 induced voltage-dependent, delayed activated K+ currents, which were augmented by an increase in intracellular cAMP and Ca2+. The chromanol derivatives 293B and 526B potently inhibited sKCNQ1 expressed in oocytes and CHO cells, but had little effect on RGT electrolyte transport. Short-circuit currents in RGT were activated by alkalinization and were decreased by acidification. In CHO cells an alkaline pH activated and an acidic pH inhibited 293B-sensitive KCNQ1 currents. Noise analysis of the cell-attached basolateral membrane of RGT indicated the presence of low-conductance (

Analysis of Piezoelectric sensor to detect flexural waves

The electromechanical transfer characteristics of adhesively bonded piezoelectric sensors are investigated. By the use of dynamic piezoelectricity theory, Mindlin plate theory for flexural wave propagation, and a multiple integral transform method, the frequency-response functions of piezoelectric sensors with and without backing materials are developed and the pressure-voltage transduction functions of the sensors calculated. The corresponding simulation results show that the sensitivity of the sensors is not only dependent on the sensors' inherent features, such as piezoelectric properties and geometry, but also on local characteristics of the tested structures and the admittance and impedance of the attached electrical circuit. It is also demonstrated that the simplified rigid mass sensor model can be used to analyze successfully the sensitivity of the sensor at low frequencies, but that the dynamic piezoelectric continuum model has to be used for higher frequencies, especially around the resonance frequency of the coupled sensor-structure vibration system.

High-performance L-band series and parallel switches using low-cost p-i-n diodes

Low-cost UHF-band p-i-n diodes are used to develop high-performance L-band series and parallel switches. To stop the rectification of large RF, signals, the diodes are biased at a large reverse-bias voltage. Parasitic elements of the diodes are tuned out using LC circuits in biasing circuits without increasing the size of the switches. (C) 2002 John Wiley Sons, Inc.

Alternative technologies for producing sterile low acid food products

Four emerging high-energy non-thermal technologies may replace or augment heating for producing sterile low-acid food products. High pressure, high-voltage pulsed electric field, high-energy ultrasound and high-intensity pulsed light are all capable of reducing bacterial spore counts under certain conditions. However, only non-continuous high pressure treatments, at temperatures higher than ambient, are currently capable of completely inactivating spores and producing sterile food products. The first three technologies also reduce the resistance of spores to inactivation by heat.

Solid-state Marx based two-switch voltage modulator for the On-Line Isotope Mass Separator accelerator at the European Organization for Nuclear Research

A new circuit topology is proposed to replace the actual pulse transformer and thyratron based resonant modulator that supplies the 60 kV target potential for the ion acceleration of the On-Line Isotope Mass Separator accelerator, the stability of which is critical for the mass resolution downstream separator, at the European Organization for Nuclear Research. The improved modulator uses two solid-state switches working together, each one based on the Marx generator concept, operating as series and parallel switches, reducing the stress on the series stacked semiconductors, and also as auxiliary pulse generator in order to fulfill the target requirements. Preliminary results of a 10 kV prototype, using 1200 V insulated gate bipolar transistors and capacitors in the solid-state Marx circuits, ten stages each, with an electrical equivalent circuit of the target, are presented, demonstrating both the improved voltage stability and pulse flexibility potential wanted for this new modulator.

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

Repetitive Solid State Pulse Modulator Based on a DC Voltage Multiplier

A newly developed solid-state repetitive high-voltage (HV) pulse modulator topology created from the mature concept of the d.c. voltage multiplier (VM) is described. The proposed circuit is based in a voltage multiplier type circuit, where a number of d.c. capacitors share a common connection with different voltage rating in each one. Hence, besides the standard VM rectifier and coupling diodes, two solid-state on/off switches are used, in each stage, to switch from the typical charging VM mode to a pulse mode with the d.c. capacitors connected in series with the load. Due to the on/off semiconductor configuration, in half-bridge structures, the maximum voltage blocked by each one is the d.c. capacitor voltage in each stage. A 2 kV prototype is described and the results are compared with PSPICE simulations.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

Optical demultiplexer based on an a-SiC:H voltage controlled device

In this paper we present results on the use of a semiconductor heterostructure based on a-SiC:H as a wavelength-division demultiplexer for the visible light spectrum. The proposed device is composed of two stacked p-i-n photodiodes with intrinsic absorber regions adjusted to short and long wavelength absorption and carrier collection. An optoelectronic characterisation of the device was performed in the visible spectrum. Demonstration of the device functionality for WDM applications was done with three different input channels covering the long, the medium and the short wavelengths in the visible range. The recovery of the input channels is explained using the photocurrent spectral dependence on the applied voltage. An electrical model of the WDM device is proposed and supported by the solution of the respective circuit equations. Short range optical communications constitute the major application field however other applications are foreseen. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, Malta

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e Tecnologia