973 resultados para SOI (silicon-on-insulator)


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An approach to transfer a high-quality Si layer for the fabrication of silicon-on-insulator wafers has been proposed based on the investigation of platelet and crack formation in hydrogenated epitaxialSi/Si0.98B0.02/Si structures grown by molecular-beam epitaxy. H-related defect formation during hydrogenation was found to be very sensitive to the thickness of the buried Si0.98B0.02 layer. For hydrogenated Si containing a 130nm thick Si0.98B0.02 layer, no platelets or cracking were observed in the B-doped region. Upon reducing the thickness of the buried Si0.98B0.02 layer to 3nm, localized continuous cracking was observed along the interface between the Si and the B-doped layers. In the latter case, the strains at the interface are believed to facilitate the (100)-oriented platelet formation and (100)-oriented crack propagation.

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Micro anchor is a kind of typical structures in micro/nano electromechanical systems (MEMS/NEMS), and it can be made by anodic bonding process, with thin films of metal or alloy as an intermediate layer. At the relative low temperature and voltage, specimens with actually sized micro anchor structures were anodically bonded using Pyrex 7740 glass and patterned crystalline silicon chips coated with aluminum thin film with a thickness comprised between 50 nm and 230 nm. To evaluate the bonding quality, tensile pulling tests have been finished with newly designed flexible fixtures for these specimens. The experimental results exhibit that the bonding tensile strength increases with the bonding temperature and voltage, but it decreases with the increase of the thickness of Al intermediate layer. This kind of thickness effect of the intermediate layer was not mentioned in the literature on anodic bonding. (C) 2008 Elsevier Ltd. All rights reserved.

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We present the design and numerical simulation results for a silicon waveguide modulator based on carrier depletion in a linear array of periodically interleaved PN junctions that are oriented perpendicular to the light propagation direction. In this geometry the overlap of the optical waveguide mode with the depletion region is much larger than in designs using a single PN junction aligned parallel to the waveguide propagation direction. Simulations predict that an optimized modulator will have a high modulation efficiency of 0.56 V.cm for a 3V bias, with a 3 dB frequency bandwidth of over 40 GHz. This device has a length of 1.86 mm with a maximum intrinsic loss of 4.3 dB at 0V bias, due to free carrier absorption. (C) 2009 Optical Society of America

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In this paper, we report the fabrication of Si-based double hetero-epitaxial SOI materials Si/gamma-Al2O3/Si. First, single crystalline gamma-Al2O3 (100) insulator films were grown epitaxially on Si(100) by LPCVD, and then, Si(100) epitaxial films were grown on gamma-Al2O3 (100)/Si(100) epi-substrates using a CVD method similar to silicon on sapphire (SOS) epitaxial growth. The Si/gamma-Al2O3 (100)/Si(100) SOI materials are characterized in detail by RHEED, XRD and AES techniques. The results demonstrate that the device-quality novel SOI materials Si/gamma-Al2O3 (100)/Si(100) has been fabricated successfully and can be used for application of MOS device.

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In this paper, we report the fabrication of Si-based double hetero-epitaxial SOI materials Si/gamma-Al2O3/Si. First, single crystalline gamma-Al2O3 (100) insulator films were grown epitaxially on Si(100) by LPCVD, and then, Si(100) epitaxial films were grown on gamma-Al2O3 (100)/Si(100) epi-substrates using a CVD method similar to silicon on sapphire (SOS) epitaxial growth. The Si/gamma-Al2O3 (100)/Si(100) SOI materials are characterized in detail by RHEED, XRD and AES techniques. The results demonstrate that the device-quality novel SOI materials Si/gamma-Al2O3 (100)/Si(100) has been fabricated successfully and can be used for application of MOS device.

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With the aim of investigating the possible integration of optoelectronic devices, epitaxial GaN layers have been grown on Si(Ill) semiconductor-on-insulator (SOI) and on Si/CoSi2/Si(111) using metalorganic chemical vapor deposition. The samples are found to possess a highly oriented wurtzite structure, a uniform thickness, and abrupt interfaces. The epitaxial orientation is determined as GaN(0001)//Si(111), GaN[1120]//Si[110], and GaN[1010]//Si[112], and the GaN layer is tensilely strained in the direction parallel to the interface. According to Rutherford backscattering/channeling spectrometry and (0002) rocking curves, the crystalline quality of GaN on Si(111) SOI is better than that of GaN on silicide. Room-temperature photoluminescence of GaN/SOI reveals a strong near-band-edge emission at 368 nm (3.37 eV) with a full width at half-maximum of 59 meV. (c) 2005 American Institute of Physics.

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We investigate the dispersion properties of nanometer-scaled silicon waveguides with channel and rib cross section around the optical fiber communication wavelength and systematically study their relationship with the key structural parameters of the waveguide. The simulation results show that the introduction of an extra degree of freedom in the rib depth enables the rib waveguide more flexible in engineering the group velocity dispersion (GVD) compared with the channel waveguide. Besides, we get the structural parameters of the waveguides that can realize zero-GVD at 1550 nm.

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A new-type silicon material, silicon on defect layer (SODL) was proved to have a very high quality surface microstructure which is necessary for commercially feasible high-density very large scale integrated circuits (VLSI). The structure of the SODL material was viewed by transmission electron microscopy. The SODL material was also proved to have a buried defect layer with an insulating resistivity of 5.7 x 10(10) OMEGA-cm.

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The development of optical network demands integrated arid multiple functionality modules to lowing cost and acquire highly reliability. Among the various contender materials to be photonic integrated circuits platform, silicon exhibits dominant characteristics and is the most promising platform materials. The paper compares the characteristics of some candidate materials with silicon and reviews recent progress in silicon based photonic integration technology. Tile challenges to silicon for optical integration for optical networking application arc also indicated.

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Defect engineering for SiO2] precipitation is investigated using He-ion implantation as the first stage of separation by implanted oxygen (STMOX). Cavities are created in Si by implantation with helium ions. After thermal annealing at different temperatures, the sample is implanted with 120keV 8.0 x 10(16) cm(-2) O ions. The O ion energy is chosen such that the peak of the concentration distribution is centred at the cavity band. For comparison, another sample is implanted with O ions alone. Cross-sectional transmission electron microscopy (XTEM), Fourier transform infrared absorbance spectrometry (FTIR) and atomic force microscopy (AFM) measurements are used to investigate the samples. The results show that a narrow nano-cavity layer is found to be excellent nucleation sites that effectively assisted SiO2 formation and released crystal lattice strain associated with silicon oxidation.

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Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

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Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.

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The effect of increasing levels of silicon on the microstructure and creep properties of high-pressure die-cast Mg-Al-Si (AS) alloys has been investigated. The morphology of the Mg2Si phase in die-cast AS alloys was found to be a function of the silicon content. The Mg2Si particles in castings with up to 1.14 wt pct Si have a Chinese script morphology. For AS21 alloys with silicon contents greater than 1.4 wt pet Si (greater than the alpha-Mg2Si binary eutectic point), some Mg2Si particles have a coarse blocky shape. Increasing the silicon content above the eutectic level results in an increase in the number of coarse faceted Mg2Si particles in the microstructure. Creep rates at 100 hours were found to decrease with increasing silicon content in AS-type alloys. The decrease in creep rate was most dramatic for silicon contents up to 1.1 wt pct. Further additions of silicon of up to 2.64 wt pct also resulted in significant decreases in creep rate.

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Studies of the optical properties and catalytic capabilities of noble metal nanoparticles (NPs), such as gold (Au) and silver (Ag), have formed the basis for the very recent fast expansion of the field of green photocatalysis: photocatalysis utilizing visible and ultraviolet light, a major part of the solar spectrum. The reason for this growth is the recognition that the localised surface plasmon resonance (LSPR) effect of Au NPs and Ag NPs can couple the light flux to the conduction electrons of metal NPs, and the excited electrons and enhanced electric fields in close proximity to the NPs can contribute to converting the solar energy to chemical energy by photon-driven photocatalytic reactions. Previously the LSPR effect of noble metal NPs was utilized almost exclusively to improve the performance of semiconductor photocatalysts (for example, TiO2 and Ag halides), but recently, a conceptual breakthrough was made: studies on light driven reactions catalysed by NPs of Au or Ag on photocatalytically inactive supports (insulating solids with a very wide band gap) have demonstrated that these materials are a class of efficient photocatalysts working by mechanisms distinct from those of semiconducting photocatalysts. There are several reasons for the significant photocatalytic activity of Au and Ag NPs. (1) The conduction electrons of the particles gain the irradiation energy, resulting in high energy electrons at the NP surface which is desirable for activating molecules on the particles for chemical reactions. (2) In such a photocatalysis system, both light harvesting and the catalysing reaction take place on the nanoparticle, and so charge transfer between the NPs and support is not a prerequisite. (3) The density of the conduction electrons at the NP surface is much higher than that at the surface of any semiconductor, and these electrons can drive the reactions on the catalysts. (4) The metal NPs have much better affinity than semiconductors to many reactants, especially organic molecules. Recent progress in photocatalysis using Au and Ag NPs on insulator supports is reviewed. We focus on the mechanism differences between insulator and semiconductor-supported Au and Ag NPs when applied in photocatalytic processes, and the influence of important factors, light intensity and wavelength, in particular estimations of light irradiation contribution, by calculating the apparent activation energies of photo reactions and thermal reactions.