Uma fonte chaveada de 50kW com correção de fator de potência para alimentação de uma tocha de plasma Indutiva utilizando técnicas de controle digital

This work deals with the development of an experimental study on a power supply of high frequency that provides the toch plasmica to be implemented in PLASPETRO project, which consists of two static converters developed by using Insulated Gate Bipolar Transistor (IGBT). The drivers used to control these keys are triggered by Digital Signal Processor (DSP) through optical fibers to reduce problems with electromagnetic interference (EMI). The first stage consists of a pre-regulator in the form of an AC to DC converter with three-phase boost power factor correction which is the main theme of this work, while the second is the source of high frequency itself. A series-resonant inverter consists of four (4) cell inverters operating in a frequency around 115 kHz each one in soft switching mode, alternating itself to supply the load (plasma torch) an alternating current with a frequency of 450 kHz. The first stage has the function of providing the series-resonant inverter a DC voltage, with the value controlled from the power supply provided by the electrical system of the utility, and correct the power factor of the system as a whole. This level of DC bus voltage at the output of the first stage will be used to control the power transferred by the inverter to the load, and it may vary from 550 VDC to a maximum of 800 VDC. To control the voltage level of DC bus driver used a proportional integral (PI) controller and to achieve the unity power factor it was used two other proportional integral currents controllers. Computational simulations were performed to assist in sizing and forecasting performance. All the control and communications needed to stage supervisory were implemented on a DSP

Implementação de processador banda base ofdma para downlink lte em fpga

This work treats of an implementation OFDMA baseband processor in hardware for LTE Downlink. The LTE or Long Term Evolution consist the last stage of development of the technology called 3G (Mobile System Third Generation) which offers an increasing in data rate and more efficiency and flexibility in transmission with application of advanced antennas and multiple carriers techniques. This technology applies in your physical layer the OFDMA technical (Orthogonal Frequency Division Multiple Access) for generation of signals and mapping of physical resources in downlink and has as base theoretical to OFDM multiple carriers technique (Orthogonal Frequency Division Multiplexing). With recent completion of LTE specifications, different hardware solutions have been developed, mainly, to the level symbol processing where the implementation of OFDMA processor in base band is commonly considered, because it is also considered a basic architecture of others important applications. For implementation of processor, the reconfigurable hardware offered by devices as FPGA are considered which shares not only to meet the high requirements of flexibility and adaptability of LTE as well as offers possibility of an implementation quick and efficient. The implementation of processor in reconfigurable hardware meets the specifications of LTE physical layer as well as have the flexibility necessary for to meet others standards and application which use OFDMA processor as basic architecture for your systems. The results obtained through of simulation and verification functional system approval the functionality and flexibility of processor implemented

Sensores e interfaces com aplicações em motor mancal

Relevant researches have been growing on electric machine without mancal or bearing and that is generally named bearingless motor or specifically, mancal motor. In this paper it is made an introductory presentation about bearingless motor and its peripherical devices with focus on the design and implementation of sensors and interfaces needed to control rotor radial positioning and rotation of the machine. The signals from the machine are conditioned in analogic inputs of DSP TMS320F2812 and used in the control program. This work has a purpose to elaborate and build a system with sensors and interfaces suitable to the input and output of DSP TMS320F2812 to control a mancal motor, bearing in mind the modularity, simplicity of circuits, low number of power used, good noise imunity and good response frequency over 10 kHz. The system is tested at a modified ordinary induction motor of 3,7 kVA to be used with a bearingless motor with divided coil

Viabilidade da Utilização de Máquinas de Indução Convencionais como Motores sem Mancais Mecânicos

Electrical Motors transform electrical energy into mechanic energy in a relatively easy way. In some specific applications, there is a need for electrical motors to function with noncontaminated fluids, in high speed systems, under inhospitable conditions, or yet, in local of difficult access and considerable depth. In these cases, the motors with mechanical bearings are not adequate as their wear give rise to maintenance. A possible solution for these problems stems from two different alternatives: motors with magnetic bearings, that increase the length of the machine (not convenient), and the bearingless motors that aggregate compactness. Induction motors have been used more and more in research, as they confer more robustness to bearingless motors compared to other types of machines building with others motors. The research that has already been carried out with bearingless induction motors utilized prototypes that had their structures of stator/rotor modified, that differ most of the times from the conventional induction motors. The goal of this work is to study the viability of the use of conventional induction Motors for the beringless motors applications, pointing out the types of Motors of this category that can be more useful. The study uses the Finite Elements Method (FEM). As a means of validation, a conventional induction motor with squirrel-cage rotor was successfully used for the beringless motor application of the divided winding type, confirming the proposed thesis. The controlling system was implemented in a Digital Signal Processor (DSP)

Acelerando algoritmos de baixo nível em visão robótica com hardware reconfigurável

A challenge that remains in the robotics field is how to make a robot to react in real time to visual stimulus. Traditional computer vision algorithms used to overcome this problem are still very expensive taking too long when using common computer processors. Very simple algorithms like image filtering or even mathematical morphology operations may take too long. Researchers have implemented image processing algorithms in high parallelism hardware devices in order to cut down the time spent in the algorithms processing, with good results. By using hardware implemented image processing techniques and a platform oriented system that uses the Nios II Processor we propose an approach that uses the hardware processing and event based programming to simplify the vision based systems while at the same time accelerating some parts of the used algorithms

Projeto e Implementação em Ambiente Foundation Fieldbus de Filtragem Estocástica Baseada em Análise de Componentes Independentes (M175)

This work considers the development of a filtering system composed of an intelligent algorithm, that separates information and noise coming from sensors interconnected by Foundation Fieldbus (FF) network. The algorithm implementation will be made through FF standard function blocks, with on-line training through OPC (OLE for Process Control), and embedded technology in a DSP (Digital Signal Processor) that interacts with the fieldbus devices. The technique ICA (Independent Component Analysis), that explores the possibility of separating mixed signals based on the fact that they are statistically independent, was chosen to this Blind Source Separation (BSS) process. The algorithm and its implementations will be Presented, as well as the results

Reaproveitamento e caracterização dos resíduos orgânicos provenientes do Programa MESA DA SOLIDARIEDADE da CEASA/RN

As an auxiliary tool to combat hunger by decreasing the waste of food and contributing for improvement of life quality on the population, CEASA/RN has released from August/03 to August/05 the program MESA DA SOLIDARIEDADE. Despite of the positive results of this program, that has already distributed around 226 tons of food, there is still food being thrown in the trash as the deliver of the same food in its natural form would be a health risk to those who would consume it and only the correct processing of this food can make it edible. This work has as a goal the reuse of solid residues of vegetal origin generated by the CEASA/RN, through the Program MESA DA SOLIDARIEDADE and the characterization of the product obtained so it might be used as a mineral complement in the human diet. To the collecting of samples (from September until December /2004) it was developed a methodology having as a reference the daily needs of mineral salts for infants at the age of seven to ten. The sample was packed in plastic bags and transported in an ambient temperature to the laboratory where it was selected, weighted, disinfected, fractionated and dried to 70ºC in greenhouse. The dry sample was shredded and stored in bottles previously sterilized. The sample in nature was weighted in the same proportion of the dry sample and it was obtained a uniform mass in a domestic processor. The physical-chemical analyses were carried out in triplicate in the samples in nature and in the dry product, being analyzed: pH, humidity, acidity and soluble solids according to IAL (1985), mineral salts contents (Ca, K, Na, Mg, P and Fe) determined by spectrophotometry of Atomic Absorption, caloric power through a calorimetric bomb and presence of fecal traces and E. coli through the colilert method (APHA, 1995). During this period the dry food a base of vegetables presented on average 5,06% of humidity, 4,62 of pH, acidity of 2,73 mg of citric acid /100g of sample, 51,45ºBrix of soluble solids, 2.323,50mg of K/100g, 299,06mg of Ca/100g, 293mg of Na/100g, 154,66mg of Mg/100g, 269,62mg of P/100g, 6,38mg of Fe/100g, caloric power of 3,691Kcal/g (15,502KJ/g) and is free of contamination by fecal traces and E..coli. The dry food developed in this research presented satisfactory characteristics regarding to its conservation, possessing low calories, constituting itself a good source of potassium, magnesium, sodium and iron that can be utilized as a food complement of these minerals

Superação da dormência de sementes de carrapicho-beiço-de-boi

Visando a obtenção de um tratamento para acelerar a germinação de sementes de Desmodium tortuosum (Sw.) DC., foram realizados dois experimentos, nos quais, segmentos unisseminados de lomentos (testemunha) foram submetidos a debulha manual; debulha manual seguida por escarificação manual empregando-se lixa n. 220; debulha mecânica (processador doméstico ); escarificação química com H2SO4 (95%) por 1,5 e 8 mim pré-aquecimento à 53°C por 4,10 e 16h em estufa com circulação forçada de ar; embebição, utilizando-se H,0 à 80°C por 1,3,5 e 10 min; H20 à 27°C por 2h e embebição com alternância térmica (H,0 à 80°C/ 5min e H20 à 13 °C / 1min) . Para a avaliação dos tratamentos foram empregados os testes de germinação, de emergência de plântulas em solo (E), de primeira contagem de germinação (PG) e de emergência (PE), índices de velocidade de germinação (I.V.G.) e de emergência (I.V.E.), e o comprimento de plântulas (CP). 0 delineamento estatístico adotado foi o inteiramente casualizado com 4 repetições de 100 (G, PG, I.V.G.) ou 20 sementes (C P) por tratamento no primeiro experimento e 4 repetições de 50 (G, PG, I.V.G.) ou 100 sementes (E, PE, I.V.E.) no segundo experimento. No primeiro experimento, os tratamentos que provocaram significativa redução da dormência (D) e, conseqüente elevação da germinação (G), em comparação à testemunha (D=82%; G=15%) foram, em ordem decrescente de eficácia: debulha e escarificação manuais (D=3%; G= 92%), debu lha mecânica (D=13%; G= 81%), embebição em H20 à 80°C por 1min (D=68%; G= 29%) e por 3 min (D=65%; G=32%). No segundo experimento, (testemunha com D=93% e G=3%) destacaram-se: debulha e escarificação manuais (D=2%; G= 93%), debulha mecânica (D = 2%; G = 87%), embebição em H20 à 80°C por 5min e alternância térmica (ambos com D=85% e G= 11%). 0s testes de vigor PC, I.V. G., I.V. E., CP, e E corroboraram esses resultados. 0s métodos de escarificação manual com lixa 220 e debulha mecânica, empregando-se processa dor, podem ser recomendados para a superação da dormência e promoção da germinação de sementes de D. tortuosum.

Aproveitamento de subprodutos da industrialização do escargot

The waste in the industries of escargot processing is very big. This is composed basically of escargot meat out of the commercialization patterns and the visceras. In this context, there is a need to take advantage to the use of these sub-products. A possibility should be drying them and transforming them in a certain form to be reused. Than, the present work has the objective of studying the reutilization of the sub-products of the escargot industrialization for by means of drying process. The samples were transformed in pastes, through a domestic processor for approximately 1 minute and compacted in trays of aluminum without perforations with three different heights (5 mm, 10 mm and 15 mm). The drying was accomplished in a tray dryer with air circulation and transverse flow at a speed of 0,2 m/s and three temperature levels (70°C, 80°C and 90ºC). A drying kinetics study was accomplished for the obtained curves and for the heat and mass transfer coefficients using experimental procedures based in an experimental planning of 22 factorial type. Microbiological and physiochemical analysis were also accomplished for the in nature and the dehydrated sub-products. In the drying process, it was observed the great importance of the external resistances to the mass transfer and heat in the period of constant tax influenced by the temperature. The evaporation taxes indicated a mixed control of the mass transfer for the case of the thickest layers. As already expected, the drying constant behavior was influenced by the temperature and thickness of the medium, increasing and decreasing. The statistical analysis of the results, in agreement with the factorial planning 22, showed that the fissures, the shrinking of the transfer area and the formation of a crust on the surface might have contributed to the differences between the practical results and the linear model proposed. The temperature and the thickness influenced significantly in the answers of the studied variables: evaporation tax and drying constant. They were obtained significant statistical models and predictive ones for evaporation tax for the meat as well as for the visceras

A novel HPF voltage source rectifier for variable speed refrigeration systems

A novel single-phase voltage source rectifier capable to achieve High-Power-Factor (HPF) for variable speed refrigeration system application, is proposed in this paper. The proposed system is composed by a single-phase high-power-factor boost rectifier, with two cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the EEC61000-3-2 standards. The digital controller for the output stage has been developed using a conventional voltage-frequency control (scalar V/f control), and a simplified stator oriented Vector control, in order to verify the feasibility and performance of the proposed digital controls for continuous temperature control applied at a refrigerator prototype.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests. (c) 2008 Elsevier B.V. All rights reserved.

Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys

The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform

Proposta e implementação de uma arquitetura reconfigurável híbrida para aplicações baseadas em fluxo de dados

The increase of applications complexity has demanded hardware even more flexible and able to achieve higher performance. Traditional hardware solutions have not been successful in providing these applications constraints. General purpose processors have inherent flexibility, since they perform several tasks, however, they can not reach high performance when compared to application-specific devices. Moreover, since application-specific devices perform only few tasks, they achieve high performance, although they have less flexibility. Reconfigurable architectures emerged as an alternative to traditional approaches and have become an area of rising interest over the last decades. The purpose of this new paradigm is to modify the device s behavior according to the application. Thus, it is possible to balance flexibility and performance and also to attend the applications constraints. This work presents the design and implementation of a coarse grained hybrid reconfigurable architecture to stream-based applications. The architecture, named RoSA, consists of a reconfigurable logic attached to a processor. Its goal is to exploit the instruction level parallelism from intensive data-flow applications to accelerate the application s execution on the reconfigurable logic. The instruction level parallelism extraction is done at compile time, thus, this work also presents an optimization phase to the RoSA architecture to be included in the GCC compiler. To design the architecture, this work also presents a methodology based on hardware reuse of datapaths, named RoSE. RoSE aims to visualize the reconfigurable units through reusability levels, which provides area saving and datapath simplification. The architecture presented was implemented in hardware description language (VHDL). It was validated through simulations and prototyping. To characterize performance analysis some benchmarks were used and they demonstrated a speedup of 11x on the execution of some applications

Simulação de reservatórios de petróleo em ambiente MPSoC

The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit, the most viable solution is the use of parallelism. Based on parallelism techniques and the progressive growth in the capacity of transistors integration in a single chip is the concept of MPSoCs (Multi-Processor System-on-Chip). MPSoCs will eventually become a cheaper and faster alternative to supercomputers and clusters, and applications developed for these high performance systems will migrate to computers equipped with MP-SoCs containing dozens to hundreds of computation cores. In particular, applications in the area of oil and natural gas exploration are also characterized by the high processing capacity required and would benefit greatly from these high performance systems. This work intends to evaluate a traditional and complex application of the oil and gas industry known as reservoir simulation, developing a solution with integrated computational systems in a single chip, with hundreds of functional unities. For this, as the STORM (MPSoC Directory-Based Platform) platform already has a shared memory model, a new distributed memory model were developed. Also a message passing library has been developed folowing MPI standard

Projeto e implementação de uma plataforma MP-SoC usando SystemC

This work presents the concept, design and implementation of a MP-SoC platform, named STORM (MP-SoC DirecTory-Based PlatfORM). Currently the platform is composed of the following modules: SPARC V8 processor, GPOP processor, Cache module, Memory module, Directory module and two different modles of Network-on-Chip, NoCX4 and Obese Tree. All modules were implemented using SystemC, simulated and validated, individually or in group. The modules description is presented in details. For programming the platform in C it was implemented a SPARC assembler, fully compatible with gcc s generated assembly code. For the parallel programming it was implemented a library for mutex managing, using the due assembler s support. A total of 10 simulations of increasing complexity are presented for the validation of the presented concepts. The simulations include real parallel applications, such as matrix multiplication, Mergesort, KMP, Motion Estimation and DCT 2D