Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits

Copyright © 2014 John Wiley & Sons, Ltd. Copyright © 2014 John Wiley & Sons, Ltd. Summary A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft-core processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10 6-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. © 2014 AIP Publishing LLC.

Parameters influencing the maximum controllable current in gate commutated thyristors

The model of interconnected numerical device segments can give a prediction on the dynamic performance of large area full wafer devices such as the Gate Commutated Thyristors (GCTs) and can be used as an optimisation tool for designing GCTs. In this study the authors evaluate the relative importance of the shallow p-base thickness, its peak concentration, the depth of the p-base and the buffer peak concentration. © The Institution of Engineering and Technology 2014.

磁性半导体GdxSi1-x和高k材料Gd2O3的研究

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

High-performance 2 mm gate width GaNHEMTs on 6H-SiC with output power of 22.4 W @ 8 GHz

Optimized AlGaN/AlN/GaN high electron mobility transistors (HEMTs) structures were grown on 2-in semi-insulating (SI) 6H-SiC substrate by metal-organic chemical vapor deposition (MOCVD). The 2-in. HEMT wafer exhibited a low average sheet resistance of 305.3 Omega/sq with a uniformity of 3.85%. The fabricated large periphery device with a dimension of 0.35 pm x 2 nun demonstrated high performance, with a maximum DC current density of 1360 mA/mm, a transconductance of 460 mS/mm, a breakdown voltage larger than 80 V, a current gain cut-off frequency of 24 GHz and a maximum oscillation frequency of 34 GHz. Under the condition of continuous-wave (CW) at 9 GHz, the device achieved 18.1 W output power with a power density of 9.05 W/mm and power-added-efficiency (PAE) of 36.4%. While the corresponding results of pulse condition at 8 GHz are 22.4 W output power with 11.2 W/mm power density and 45.3% PAE. These are the state-of-the-art power performance ever reported for this physical dimension of GaN HEMTs based on SiC substrate at 8 GHz. (c) 2008 Elsevier Ltd. All rights reserved.

Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation

The interface dipole and its role in the effective work function (EWF) modulation by Al incorporation are investigated. Our study shows that the interface dipole located at the high-k/SiO2 interface causes an electrostatic potential difference across the metal/high-k interface, which significantly shifts the band alignment between the metal and high-k, consequently modulating the EWF. The electrochemical potential equalization and electrostatic potential methods are used to evaluate the interface dipole and its contribution. The calculated EWF modulation agrees with experimental data and can provide insight to the control of EWF in future pMOS technology.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

Broadband polarization-insensitive semiconductor optical amplifier gate with tensile InGaAs quasi-bulk and compressively strained InGaAs wells

A novel wideband polarization-insensitive semiconductor optical amplifier (SOA) gate containing compressively strained InGaAs quantum wells and tensile-strained InGaAs quasi-bulk layers is developed. The fabricated SOA gates have a wide 3-dB optical bandwidth of 102 nm, less than 0.8-dB polarization sensitivity, more than 50-dB extinction ratio, and less than 75-mA fiber-to-fiber lossless operating current. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

ac gate-induced Fano resonance and peak splitting of conductance in a quantum dot

We have investigated the conductance of a quantum dot system suffering an anti-symmetric ac gate voltage which induces the transition between dot levels in the linear regime at zero temperature in the rotating wave approximation. Interesting Fano resonances appear on one side of the displaced resonant tunnelling peaks for the nonresonant case or the peak splitting for the resonant case. The line shape of conductance (vs Fermi energy) near each level of the quantum dot can be decomposed into two profiles: a Breit-Wigner peak and a Fano profile, or a Breit-Wigner peak and a dip in both cases.

Effect of the oxygen concentration on the properties of Gd2O3 thin films

Gd2O3 thin films were deposited on Si (100) substrates at 650degreesC by a magnetron sputtering system under different Ar/O-2 ratios of 6:1, 4:1 and 2:1. The effect of the oxygen concentration on the properties of oxide thin films was investigated by X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscopy and capacitance-voltage (C-V)measurement. X-ray diffraction shows that the structure of oxide films changed from the monoclinic Gd2O3 phase to cubic Gd2O3 phase when the oxygen concentration increased. According to C-V measurement, the dielectric constant value of the samples deposited at different Ar/O-2 ratios is about 12. (C) 2004 Elsevier B.V. All rights reserved.

Theoretical analysis of gate voltage-controlled subband states in an AlxGa1-xN/GaN heterostructure

The subband structure and inter-subband transition as a function of gate voltage are determined by solving the Schrodinger and Poisson equations self-consistently in an AlxGa1-xN/GaN heterostructure. Different aluminum mole fraction and thickness of AlxGa1-xN barrier are considered. Calculation results show that energy difference between the first and second subband covers a wide range (from several tens to hundreds milli-electron volt) by applying different gate voltage, which corresponds to the midinfrared and long-wave infrared wavelength scope. Furthermore, such a modulation on the subband transition energy is much more pronounced for the structure with thin barrier. When the applied positive gate voltage is increased, the triangle well formed at the interface turns to be deeper and narrower, which enhances the confinement for electrons. As a result, the overlap between electron wave function at two subbands increases, and thus the optical intersubband transition also enhances its intensity. This tendency is in good agreement with the available data in the literature. (c) 2005 Elsevier B.V. All rights reserved.

Effect of the technology of implanting nitrogen into buried oxide on the radiation hardness of the top gate oxide for partially depleted SOIPMOSFET

The effect of implanting nitrogen into buried oxide on the top gate oxide hardness against total irradiation does has been investigated with three nitrogen implantation doses (8 x 10(15), 2 x 10(16) and 1 x 10(17) cm(-2)) for partially depleted SOI PMOSFET. The experimental results reveal the trend of negative shift of the threshold voltages of the studied transistors with the increase of nitrogen implantation dose before irradiation. After the irradiation with a total dose of 5 x 10(5) rad(Si) under a positive gate voltage of 2V, the threshold voltage shift of the transistors corresponding to the nitrogen implantation dose 8 x 10(15) cm(-2) is smaller than that of the transistors without implantation. However, when the implantation dose reaches 2 x 10(16) and 1 x 10(17) cm(-2), for the majority of the tested transistors, their top gate oxide was badly damaged due to irradiation. In addition, the radiation also causes damage to the body-drain junctions of the transistors with the gate oxide damaged. All the results can be interpreted by tracing back to the nitrogen implantation damage to the crystal lattices in the top silicon.