Spatially resolved diagnostics on a micro atmospheric pressure plasma jet

Despite enormous potential for technological applications, fundamentals of stable non-equilibrium micro-plasmas at ambient pressure are still only partly understood. Micro-plasma jets are one sub-group of these plasma sources. For an understanding it is particularly important to analyse transport phenomena of energy and particles within and between the core and effluent of the discharge. The complexity of the problem requires the combination and correlation of various highly sophisticated diagnostics yielding different information with an extremely high temporal and spatial resolution. A specially designed rf microscale atmospheric pressure plasma jet (µ-APPJ) provides excellent access for optical diagnostics to the discharge volume and the effluent region. This allows detailed investigations of the discharge dynamics and energy transport mechanisms from the discharge to the effluent. Here we present examples for diagnostics applicable to different regions and combine the results. The diagnostics applied are optical emission spectroscopy (OES) in the visible and ultraviolet and two-photon absorption laser-induced fluorescence spectroscopy. By the latter spatially resolved absolutely calibrated density maps of atomic oxygen have been determined for the effluent. OES yields an insight into energy transport mechanisms from the core into the effluent. The first results of spatially and phase-resolved OES measurements of the discharge dynamics of the core are presented.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Extrinsic parameter extraction and RF modelling of CMOS

An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation. (C) 2003 Elsevier Ltd. All rights reserved.

Unusual voltammetry of the reduction of O-2 in [C(4)dmim][N(Tf)(2)] reveals a strong interaction of O-2(center dot-) with the [C(4)dmim](+) cation

Voltammetric studies of the reduction of oxygen in the room temperature ionic liquid [C(4)dmim][N(Tf)(2)] have revealed a significant positive shift in the back peak potential, relative to that expected for a simple electron transfer. This shift is thought to be due to the strong association of the electrogenerated superoxide anion with the solvent cation. In this work we quantitatively simulate the microdisc electrode voltammetry using a model based upon a one-electron reduction followed by a reversible chemical step, involving the formation of the [C(4)dmim](+)center dot center dot center dot O-2(center dot-) ion-pair, and in doing so we extract a set of parameters completely describing the system. We have simulated the voltammetry in the absence of a following chemical step and have shown that it is impossible to simultaneously fit both the forward and reverse peaks. To further support the parameters extracted from fitting the experimental voltammetry, we have used these parameters to independently simulate the double step chronoamperometric response and found excellent agreement. The parameters used to describe the association of the O-2(center dot-) with the [C(4)dmim](+) were k(f) = 1.4 x 10(3) s(-1) for the first-order rate constant and K-eq = 25 for the equilibrium constant.

Electrochemical reduction of benzoic acid and substituted benzoic acids in some room temperature ionic liquids

Using cyclic voltammetry, the electrochemical reduction of benzoic acid (BZA) has been studied at Pt and Au microelectrodes (10 and 2 mu m diameter) in six room temperature ionic liquids (RTILs), namely [C(2)mim][NTf2], [C(4)mim][NTf2], [C(4)mpyrr][NTf2], [C(4)mim][BF4], [C(4)mim][NO3], and [C(4)mim][PF6] (where [C(n)mim](+) = 1-alkyl-3-methylimidazolium, [NTf2](-) = bis(trifluoromethylsulfonyl)imide, [C(4)mpyrr](+) = N-butyl-N-methylpyrrolidinium, [BF4](-) = tetrafluoroborate, [NO3](-) = nitrate, and [PF6](-) = hexafluorophosphate). In all cases, a main reduction peak was observed, assigned to the reduction of BZA in a CE mechanism, where dissociation of the acid takes place before electron transfer to the dissociated proton. One anodic peak was observed on the reverse sweep, assigned to the oxidation of adsorbed hydrogen, and a reductive

Modulating the selectivity for CO and butane oxidation over heterogeneous catalysis through amorphous catalyst coatings

The preparation of porous films directly deposited onto the surface of catalyst particles is attracting increasing attention. We report here for the first time a method that can be carried out at ambient pressure for the preparation of porous films deposited over 3 mm diameter catalyst particles of silica-supported Pt-Fe. Characterization of the sample prepared at ambient pressure (i.e., open air, OA) and its main structural differences as compared with a Na-A (LTA) coated catalyst made using an autoclave-based method are presented. The OA-coated material predominantly exhibited an amorphous film over the catalyst surface with between 4 and 13% of crystallinity as compared with fully crystallized LTA zeolite crystals. This coated sample was highly selective for CO oxidation in the presence of butane with no butane oxidation observed up to 350 degrees C. This indicates, for the first time, that the presence of a crystalline membrane is not necessary for the difference in light off temperature between CO and butane to be achieved and that amorphous films may also produce this effect. An examination of the space velocity dependence and adsorption of Na+ on the catalysts indicates that the variation in CO and butane oxidation activity is not caused by site blocking predominantly, although the Pt activity was lowered by contact with this alkali.

Electrode kinetics and mechanism of iodine reduction in the room-temperature ionic liquid [C(4)mim][NTf2]

The fast electrochemical reduction of iodine in the RTIL 1-butyl-3-methylimidazolium bis(trifluoromethyl-sulfonyl)imide, [C(4)mim][NTf2], is reported and the kinetics and mechanism of the process elucidated. Two reduction peaks were observed. The first reduction peak is assigned to the process

Comparison between fluid simulations and experiments in inductively coupled argon/chlorine plasmas

Comparisons of 2D fluid simulations with experimental measurements of Ar/Cl-2 plasmas in a low-pressure inductively coupled reactor are reported. Simulations show that the wall recombination coefficient of Cl atom (gamma) is a crucial parameter of the model and that neutral densities are very sensitive to its variations. The best agreement between model and experiment is obtained for gamma = 0.02, which is much lower than the value predicted for stainless steel walls (gamma = 0.6). This is consistent with reactor wall contaminations classically observed in such discharges. The electron density, negative ion fraction and Cl atom density have been investigated under various conditions of chlorine and argon concentrations, gas pressure and applied rf input power. The plasma electronegativity decreases with rf power and increases with chlorine concentration. At high pressure, the power absorption and distribution of charged particles become more localized below the quartz window. Although the experimental trends are well reproduced by the simulations, the calculated charged particle densities are systematically overestimated by a factor of 3-5. The reasons for this discrepancy are discussed in the paper.