Investigating the role of knowledge management at various maturity levels of project management office

This thesis is an exploratory study to scrutinise Project Knowledge Management in Project-Based Organisations, specifically in the Project Management Office (PMO). It is the first attempt to investigate the maturity of Project Management, from a Knowledge Management perspective. The findings of this study address multiple Knowledge Management processes and practices to both assess the level of Knowledge Management Maturity in PMOs, and improve the capability of Project Knowledge Management in Project-based Organisations. This research significantly contributes to bridge the current gap in the existing Project Management Maturity Models.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device

Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the ON-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

Escritório de projetos na Câmara dos Deputados : estudo de caso - interação entre os escritórios setoriais e o Escritório Corporativo na Câmara dos Deputados

Este trabalho visa estudar o modelo de escritórios de projeto da Câmara dos Deputados, objetivando compreender como é a atual interação entre os escritórios e sugerir melhorias nesta interação. O referencial teórico adotado discute conceitos relacionados a gestão de projetos e a escritórios de projeto, identificando possíveis atribuições e tipos existentes. Para a análise deste estudo de caso, foi feita uma contextualização do surgimento da Gestão Estratégica de Câmara dos Deputados, bem como a apresentação do atual modelo de escritórios de projeto da Casa. A pesquisa realizada em todos os escritórios da Casa foi a qualitativa. Os resultados apresentam as dificuldades encontradas atualmente, em especial no uso da metodologia adotada pela Câmara, e apresenta sugestões feitas pelos próprios entrevistados. Conclui-se que há um desalinhamento entre os escritórios, porém um grande interesse em encontrar um equilíbrio entre o uso da metodologia e nos resultados obtidos pelo seu uso.

Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation

The interface dipole and its role in the effective work function (EWF) modulation by Al incorporation are investigated. Our study shows that the interface dipole located at the high-k/SiO2 interface causes an electrostatic potential difference across the metal/high-k interface, which significantly shifts the band alignment between the metal and high-k, consequently modulating the EWF. The electrochemical potential equalization and electrostatic potential methods are used to evaluate the interface dipole and its contribution. The calculated EWF modulation agrees with experimental data and can provide insight to the control of EWF in future pMOS technology.

Silicon-on-insulating multi-layers for total-dose irradiation hardness

Silicon-on-insulating multi-layer (SOIM) materials were fabricated by co-implantation of oxygen and nitrogen ions with different energies and doses. The multilayer microstructure was investigated by cross-sectional transmission electron microscopy. P-channel metal-oxide-semiconductor (PMOS) transistors and metal-semiconductor-insulator-semiconductor (MSIS) capacitors were produced by these materials. After the irradiated total dose reaches 3 x 10(5) rad (Si), the threshold voltage of the SOIM-based PMOS transistor only shifts 0.07 V, while thin silicon-on-insulating buried-oxide SIMOX-based PMOS transistors have a shift of 1.2V, where SIMOX represents the separated by implanted oxygen. The difference of capacitance of the SOIM-based MSIS capacitors before and after irradiation is less than that of the thin-box SIMOX-based MSIS capacitor. The results suggest that the SOIM materials have a more remarkable irradiation tolerance of total dose effect, compared to the thin-buried-oxide SIMOX materials.

Formation of total-dose-radiation hardened materials by sequential oxygen and nitrogen implantation and multi-step annealing

Separation by implantation of oxygen and nitrogen (SIMON) silicon-on-insulator (SOI) materials were fabricated by sequential oxygen and nitrogen implantation with annealing after each implantation. Analyses of SIMS, XTEM and HRTEM were performed. The results show that superior buried insulating multi-layers were well formed and the possible mechanism is discussed. The remarkable total-dose irradiation tolerance of SIMON materials was confirmed by few shifts of drain leakage current-gate source voltage (I-V) curves of PMOS transistors fabricated on SIMON materials before and after irradiation.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

An ambient proof and wide tuning range LC VCO with automatic amplitude control for tuner applications

This paper represents a LC VCO with AAC (Auto Amplitude Control), in which PMOS FETs are used as active components, and the varactors are directly connected to ground to widen Kvco linear range. The AAC circuitry adds little noise to the VCO and provides it with robust performance over a wide temperature and carrier frequency range. The VCO is fabricated in 50-GHz 0.35-mu m SiGe BiCMOS process. The measurement results show that it has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole circuit draws 6.6-mA current from 5.0-V supply.

A 1.1GHz LC VCO with Automatic Amplitude Control for Tuner Applications

This paper presents an LC VCO with auto-amplitude control （AAC）, in which pMOS FETs are used,and the varactors are directly connected to ground to widen the linear range of Kvco. The AAC circuitry adds little noise to the VCO but provides it with robust performance over a wide temperature and carrier frequency range.The VCO is fabricated in a chartered 50GHz 0.35μm SiGe BiCMOS process. The measurements show that it has - 127. 27dBc/Hz phase noise at 1MHz offset and a linear gain of 32.4MHz/V between 990MHz and 1.14GHz.The whole circuit draws 6. 6mA current from 5V supply.

Total Dose Radiation-Hard 0. SOI CMOS Transistors and ASIC

This paper presents the total dose radiation performance of 0. S^m SOI CMOS devices fabricated with full dose SIMOX technology. The radiation performance is characterized by threshold voltage shifts and leakage currents of transistors and standby currents of ASIC as functions of the total dose up to 500krad(Si) .The experimental results show that the worst case threshold voltage shifts of front channels are less than 320mV for pMOS transistors under off-gate radiation bias at lMrad(Si) and less than 120mV for nMOS transistors under on-gate radiation bias. No significant radiation-induced leakage current is observed in transistors to lMrad(Si). The standby currents of ASIC are less than the specification of 5μA over the total dose range of 500krad(Si).

全耗尽CMOS/SOI工艺

对全耗尽CMOS/SOI工艺进行了研究，成功地开发出成套全耗尽CMOS/SOI抗辐照工艺，其关键工艺技术包括：氮化H2-O2合成薄栅氧、双栅和注Ge硅化物等技术，经过工艺设计，获得性能良好的抗辐照CMOS/SOI器件和电路（包括101级环振、2000门门海阵列等）其中，nMOS:Vt=0.7V,Vds=4.5-5.2V,μeff=465cm^2/（V·S），PMOS：Vt=-0.8V,Vds=-5～-6.3V,μeff=264cm^2/(V·S），当工作电压为5V时，0.8μm环振单级延迟为45ps。

五种天然低聚糖及其硫酸酯衍生物抗病毒活性研究

本文直接针对当前严重的世界性问题－病毒传染性疾病，开展了五种天然低聚糖及其硫酸酯衍生物的制备、抗病毒活性研究以及具抗疱疹病毒活性低聚糖硫酸酯作用机制的初步探讨。中药的结构修饰是中药现代化的重要内容，本研究的开展结合了药学、药理学和构效学，进一步丰富了硫酸酯化糖类抗病毒活性研究，有助于获得抗病毒活性新型药物以用于病毒引起的各类疾病，具有重要的理论和应用意义。1。分别从多花黄精以及与之在种属上有着由近及远关系的大玉竹、天冬、魔芋（酶解干粉）和香菇（子实体）中用类似程序提取了五种低聚糖样品，分别命名为Pcos、Pmos、Acos、Apkos、Leos。单糖组成分析、凝胶柱层析、红外光谱分析以及基体辅助激光解吸-飞行时间质谱分析的结果表明五种样品属于分子量比较接近、单糖组成各异、糖链骨架结构不同的低聚糖。这为后面不同糖链骨架结构的低聚糖硫酸酯的制备、探讨低聚糖硫酸酯衍生物糖链结构与抗病毒活性的关系建立了基础。从香菇子实体中用酶法制备低糖为首次报道。2。采用氯磺酸-吡啶法分别制备了五种天然低聚会糖的硫酸酯衍生物，分别命名为S-Pcos、S-Pmos、S-Acos、S-Apkos、S-Leos，经硫含量分析、Biol-Gel P4 凝胶柱层析、红外光谱分析证明该方法成功地向低聚糖中引入了硫酸基团，为开展天然低聚糖及其硫酸酯的抗病毒活性研究准备了必备的材料。3。利用细胞病变抑制法、中性红染色法、病毒空斑抑制法开展了五种低聚糖及其硫酸酯的体外抗HSV-2活性研究，结果都表明五种天然低聚糖本身没有抗HSV-2活性，除S-Acos之外的四种不同糖链骨架结构的低聚糖硫酸酯产生大小不同的活性， 说明硫酸酯低聚糖的抗病毒活性具有普遍的意义，这就大大扩大了药源，也为新的抗病毒活性药物筛选提供了新的思路和途径。S-Acos没有抗HSV-2活性，可能是因为低聚糖硫酸酯的抗病毒活性还存在硫酸基团以外的其它因素在起作用。五种低聚糖硫酸酯能抑制乙型肝炎抗原表达，说明低聚糖硫酸酯可能具有广谱抗病毒活性，有很大的应用前景。大玉竹、天冬、魔芋低聚糖及其硫酸酯的抗病毒活性研究未见报道。四种具抗HSV-2活性的低聚糖硫酸酯中，以S-Pmos的抗HSV-2活性最好，具有潜在抗病毒药物开发应用价值，值得进一步研究开发。4。初步探讨了低聚糖硫酸酯的抗病毒作用机制，由不同时间加药实验结果推测四种低聚糖硫酸硫酯具有类似的作用机制，可能作用于HSV-2与细胞的吸附阶段，不能抑制病毒在细胞内的复制过程；低聚糖硫酸酯的作用对象为病毒；对病毒毒力的影响实验和撤药实验说明四种低聚硫酸酯不能杀灭HSV-2，仅起抑制作用。作用机制的研究不仅进一步明确了四种低聚糖硫酸酯的抗HSV-2活性，还为今后开发和临床应用该类潜在性抗病毒药物提供了实验基础和依据。